Power device structures and methods

• US 8,304,329 B2
• Filed: 11/25/2009
• Issued: 11/06/2012
• Est. Priority Date: 12/01/2008
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Zeng, Jun, Darwish, Mohamed N.
• Primary Examiner(s): Lee, Eugene
• Application Number:
  US12/626,523
• Publication Number:
  US 20100219468A1
• Time in Patent Office: 1,077 Days
• Field of Search: 438/506, 438/514, 257/340, 257/409, 257/328
• US Class Current: 438/506
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1079 with insulated gate
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling.

Claims

1. A method for operating a vertical semiconductor device, comprising:

gating emission of first-type majority carriers from a source region using a control gate;

routing said majority carriers through an induced drain extension in a second-type semiconductor drift region;

said induced drain extension comprising an excess of said first-type carriers along the face of a dielectric trench in contact with said semiconductor drift region, said excess being electrostatically induced by permanent charges; and

reducing capacitance between said control gate and said semiconductor drift region by use of a conductive shield beneath said control gate.

3. The method of claim 1, wherein the maximum width of said shield is less than the maximum width of said gate.

4. The method of claim 1, wherein both said shield and said gate lie entirely within said trench, and said gate is wider than said shield.

5. The method of claim 1, wherein said shield, but not said gate, lies entirely within said trench.

6. The method of claim 1, wherein said majority carriers are electrons.

2. A method for operating a vertical semiconductor device, comprising:

gating emission of first-type majority carriers from a source region using a control gate;

routing said majority carriers through an induced drain extension in a second-type semiconductor drift region;

said induced drain extension comprising an excess of said first-type carriers along the face of a dielectric trench in contact with said semiconductor drift region, said excess being electrostatically induced by permanent charges; and

reducing capacitance between said control gate and said semiconductor drift region by use of a conductive shield beneath said control gate;

wherein said permanent charges are cesium ions.

7. A method for operating a vertical semiconductor device, comprising:

gating emission of first-type majority carriers from a source region using a control gate;

routing said majority carriers through an induced drain extension in a second-type semiconductor drift region;

said induced drain extension comprising an excess of said first-type carriers along the face of a dielectric trench in contact with said semiconductor drift region, said excess being electrostatically induced by permanent charges; and

reducing capacitance between said control gate and said semiconductor drift region by use of a conductive shield beneath said control gate;

wherein said majority carriers are electrons, and said second conductivity type is p-type.