Active matrix substrate having channel protection film covering transistor channel, and display apparatus and/or, television receiver including same

• US 8,304,769 B2
• Filed: 12/05/2006
• Issued: 11/06/2012
• Est. Priority Date: 03/15/2006
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Tsubata, Toshihide, Takeuchi, Masanori
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Henry, Caleb
• Application Number:
  US12/224,679
• Publication Number:
  US 20090065778A1
• Time in Patent Office: 2,163 Days
• Field of Search: 349/38, 257/71, 257/72, 257/E27.111, 257/E27.113, 257/E29.151, 257/59
• US Class Current: 257/59
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

An active matrix substrate of the present invention is arranged so that each pixel area has a transistor and a capacity electrode which is able to function as an electrode of a capacity. The active matrix substrate includes a conductor which is provided in a layer below the capacity electrode and is able to function as the other electrode of the capacity. The gate electrode of each transistor and a gate insulating film covering the conductor have a thin section with reduced thickness, in an on-conductor area overlapping the conductor. At least a part of the thin section overlaps the capacity electrode. In this way, the active matrix substrate which can reduce inconsistency in capacitance values of capacities (e.g. a storage capacitor, a capacity for controlling an electric potential of a pixel electrode, and a capacity which can function as both of them) provided in the substrate.

Claims

1. An active matrix substrate comprising:

a transistor;

a pixel electrode electrically connected to the transistor;

a conductor provided in a layer below the pixel electrode and an insulating film interposed between at least the pixel electrode and the conductor, the pixel electrode overlapping the conductor;

wherein the insulating film comprises a thin section and a non-thin section which is thicker than the thin section;

wherein the pixel electrode includes (a) a part overlapping the thin section and the conductor, and (b) a part overlapping the non-thin section and the conductor, and wherein no other electrode is located between the pixel electrode and the conductor in the area where the pixel electrode overlaps the thin section;

wherein (i) the thin section includes a part of a gate insulating film and a part of a channel protection film that contact with each other, and (ii) the non-thin section includes another part of said gate insulating film and another part of said channel protection film that contact with each other, and (iii) said gate insulating film covers a gate electrode of the transistor, and (iv) said channel protection film covers a channel of the transistor, and wherein said gate insulating film that is present in both the non-thin section and the thin section is also provided in the transistor between at least the gate electrode and a drain electrode of the transistor; and

wherein the thin section is formed so that the non-thin section surrounds the thin section.

9. A display apparatus comprising the active matrix substrate as defined in claim 1.

10. A television receiving comprising the display apparatus of claim 9;

and a tuner section receiving television broadcast.

2. An active matrix substrate comprising:

a transistor;

a pixel electrode electrically connected to the transistor;

a conductor provided in a layer below the pixel electrode and an insulating film interposed between at least the pixel electrode and the conductor, the pixel electrode overlapping the conductor;

wherein the insulating film comprises a thin section and a non-thin section which is thicker than the thin section;

wherein the pixel electrode includes (a) a part overlapping the thin section and the conductor, and (b) a part overlapping the non-thin section and the conductor;

wherein (i) the thin section includes a part of a gate insulating film and a part of a channel protection film that contact with each other, and (ii) the non-thin section includes another part of said gate insulating film and another part of said channel protection film that contact with each other, and (iii) said gate insulating film covers a gate electrode of the transistor, and (iv) said channel protection film covers a channel of the transistor, and wherein said gate insulating film that is present in both the non-thin section and the thin section is also provided in the transistor between at least the gate electrode and a drain electrode of the transistor;

wherein the pixel electrode overlaps the entirety of the thin section; and

wherein the conductor is a storage capacity wiring not proximate a gate of the transistor.

3. An active matrix substrate comprising:

a transistor;

a pixel electrode electrically connected to the transistor;

a conductor provided in a layer below the pixel electrode and an insulating film interposed between at least the pixel electrode and the conductor, the pixel electrode overlapping the conductor;

wherein the insulating film comprises a thin section and a non-thin section which is thicker than the thin section;

wherein the pixel electrode includes (a) a part overlapping the thin section and the conductor, and (b) a part overlapping the non-thin section and the conductor;

wherein (i) the thin section includes a part of a gate insulating film and a part of a channel protection film that contact with each other, and (ii) the non-thin section includes another part of said gate insulating film and another part of said channel protection film that contact with each other, and (iii) said gate insulating film covers a gate electrode of the transistor, and (iv) said channel protection film covers a channel of the transistor, and wherein said gate insulating film that is present in both the non-thin section and the thin section is also provided in the transistor between at least the gate electrode and a drain electrode of the transistor; and

wherein the pixel electrode is electrically connected with a drain electrode of the transistor.

4. An active matrix substrate comprising:

a transistor;

a pixel electrode electrically connected to the transistor;

a conductor provided in a layer below the pixel electrode and an insulating film interposed between at least the pixel electrode and the conductor, the pixel electrode overlapping the conductor;

wherein the insulating film comprises a thin section and a non-thin section which is thicker than the thin section;

wherein the pixel electrode includes (a) a part overlapping the thin section and the conductor, and (b) a part overlapping the non-thin section and the conductor;

wherein (i) the thin section includes a part of a gate insulating film and a part of a channel protection film that contact with each other, and (ii) the non-thin section includes another part of said gate insulating film and another part of said channel protection film that contact with each other, and (iii) said gate insulating film covers a gate electrode of the transistor, and (iv) said channel protection film covers a channel of the transistor, and wherein said gate insulating film that is present in both the non-thin section and the thin section is also provided in the transistor between at least the gate electrode and a drain electrode of the transistor; and

wherein the conductor is part of a storage capacity wiring.

7. The active matrix substrate as defined in claim 4, wherein the storage capacity wiring overlaps a round edge of the pixel electrode.

8. The active matrix substrate as defined in claim 4, wherein the pixel electrode comprises (a) an edge extending along a data signal line connected to a source electrode of the transistor, and (b) an edge facing that edge, and wherein the storage capacity wiring overlaps both of these edges.

5. An active matrix substrate comprising:

a transistor;

a pixel electrode electrically connected to the transistor;

a conductor provided in a layer below the pixel electrode and an insulating film interposed between at least the pixel electrode and the conductor, the pixel electrode overlapping the conductor;

wherein the insulating film comprises a thin section and a non-thin section which is thicker than the thin section;

wherein the pixel electrode includes (a) a part overlapping the thin section and the conductor, and (b) a part overlapping the non-thin section and the conductor;

wherein (i) the thin section includes a part of a gate insulating film and a part of a channel protection film that contact with each other, and (ii) the non-thin section includes another part of said gate insulating film and another part of said channel protection film that contact with each other, and (iii) said gate insulating film covers a gate electrode of the transistor, and (iv) said channel protection film covers a channel of the transistor, and wherein said gate insulating film that is present in both the non-thin section and the thin section is also provided in the transistor between at least the gate electrode and a drain electrode of the transistor; and

wherein a flattening film is provided at the non-thin section, the flattening film being ablated at the thin section.

6. An active matrix substrate comprising:

a transistor;

a pixel electrode electrically connected to the transistor;

a conductor provided in a layer below the pixel electrode and an insulating film interposed between at least the pixel electrode and the conductor, the pixel electrode overlapping the conductor;

wherein the insulating film comprises a thin section and a non-thin section which is thicker than the thin section;

wherein the pixel electrode includes (a) a part overlapping the thin section and the conductor, and (b) a part overlapping the non-thin section and the conductor;

wherein (i) the thin section includes a part of a gate insulating film and a part of a channel protection film that contact with each other, and (ii) the non-thin section includes another part of said gate insulating film and another part of said channel protection film that contact with each other, and (iii) said gate insulating film covers a gate electrode of the transistor, and (iv) said channel protection film covers a channel of the transistor, and wherein said gate insulating film that is present in both the non-thin section and the thin section is also provided in the transistor between at least the gate electrode and a drain electrode of the transistor; and

wherein SOG (spin on glass) film comprising SOG material is included at the non-thin section, the SOG film is ablated at the thin section.

11. An active matrix substrate comprising:

a transistor;

a first pixel electrode electrically connected to the transistor;

a first conductor provided in a layer below the first pixel electrode and an insulating film interposed between at least the first pixel electrode and the first conductor, the first pixel electrode overlapping the first conductor;

a second pixel electrode;

a second conductor provided in a layer below the second pixel electrode and an insulating film interposed between at least the second pixel electrode and the second conductor, the second pixel electrode overlapping the second conductor;

wherein the first and second pixel electrodes are provided so as to correspond to a pixel;

wherein the insulating film comprises a thin section and a non-thin section which is thicker than the thin section;

wherein the first pixel electrode includes (a) a part overlapping the thin section and the first conductor, and (b) a part overlapping the non-thin section and the first conductor; and

wherein (i) the thin section includes a part of a gate insulating film and a part of a channel protection film that contact with each other, and (ii) the non-thin section includes another part of said gate insulating film and another part of said channel protection film that contact with each other, and (iii) said gate insulating film covers a gate electrode of the transistor, and (iv) said channel protection film covers a channel of the transistor, and wherein said gate insulating film that is present in both the non-thin section and the thin section is also provided in the transistor between at least the gate electrode and a drain electrode of the transistor.

12. A display apparatus comprising the active matrix substrate as defined in claim 11, wherein said pixel includes a first area corresponding to the first pixel electrode and a second area corresponding to the second pixel electrode;

and halftone display is performed by setting a brightness of the first area and a brightness of the second area to different values.

13. The display apparatus of claim 12, wherein the second pixel electrode is connected to another transistor electrically;

and the first and second conductors are parts of first and second storage capacity wirings respectively, and are able to individually control electric potentials of the first and second storage capacity wirings, and electric potentials of the first and second pixel electrodes are individually controlled by this potential control.

14. The display apparatus of claim 13,

wherein, the electric potential of the first storage capacity wiring is controlled in such a way that the electric potential increases after each of the transistors is turned off and an increased state continues until each of the transistors is turned off in a next frame, and the electric potential of the second storage capacity wiring is controlled in such a way that the electric potential decreases after each of the transistors is turned off and a decreased state continues until each of the transistors is turned off in a next frame, or

the electric potential of the first storage capacity wiring is controlled in such a way that the electric potential decreases after each of the transistors is turned off and a decreased state continues until each of the transistors is turned off in a next frame, and the electric potential of the second storage capacity wiring is controlled in such a way that the electric potential increases after each of the transistors is turned off and an increased state continues until each of the transistors is turned off in a next frame.

15. The display apparatus as defined in claim 14,

wherein, an increase in the electric potential of the first storage capacity wiring occurs one horizontal period before or after a decrease in the electric potential of the second storage capacity wiring, or a decrease in the electric potential of the first storage capacity wiring occurs one horizontal period before or after an increase in the electric potential of the second storage capacity wiring.