Trench-based power semiconductor devices with increased breakdown voltage characteristics

• US 8,304,829 B2
• Filed: 03/20/2009
• Issued: 11/06/2012
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Challa, Ashok
• Primary Examiner(s): Li, Meiya
• Application Number:
  US12/408,552
• Publication Number:
  US 20100140695A1
• Time in Patent Office: 1,327 Days
• Field of Search: 257/301, 257/302, 257/329, 257/330, 257/331, 257/334, 257/340, 257/341, 257/E29.257, 257/E29.262, 257/E29.264, 257/E29.129, 257/E21.384, 257/E21.396, 257/E21.419, 438/270, 438/272, 438/257, 438/259, 438/243, 438/244, 438/386, 438/387
• US Class Current: 257/334
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Claims

1. A semiconductor device comprising:

a first trench extending into an epitaxial layer and including a first shield electrode and a gate electrode disposed therein, the first shield electrode of the first trench being electrically insulated from the gate electrode;

a source pad electrically coupled to the first shield electrode of the first trench;

a gate pad electrically coupled to the gate electrode of the first trench; and

a second trench extending into the epitaxial layer and having at least a portion disposed directly under the gate pad between the gate pad and a substrate, the second trench including a second shield electrode disposed therein, the second shield electrode having a vertical length greater than a vertical length of the first shield electrode.

2. The semiconductor device of claim 1, wherein the second shield electrode of the second trench is electrically coupled to the source pad.

3. The semiconductor device of claim 1, wherein the second shield electrode of the second trench is electrically floating.

4. The semiconductor device of claim 1, wherein the gate electrode of the first trench is a first gate electrode, the second trench includes a second gate electrode vertically stacked over the second shield electrode of the second trench, the second shield electrode of the second trench being electrically insulated from the second gate electrode of the second trench, the second gate electrode of the second trench is electrically coupled to the gate pad.

5. The semiconductor device of claim 1, wherein the second shield electrode of the second trench is electrically coupled to the source pad,

the semiconductor device further comprising:

a third trench including an electrically floating electrode disposed therein.

6. The semiconductor device of claim 1, further comprising:

a third trench disposed directly under the gate pad and adjacent to the second trench; and

a mesa of semiconductor material disposed between the second trench and the third trench and being an electrically floating mesa.

7. The semiconductor device of claim 1, further comprising:

a third trench disposed directly under the gate pad and adjacent to the second trench, the third trench including an electrically floating electrode disposed therein.

8. The semiconductor device of claim 1, further comprising:

a third trench disposed directly under the gate pad and adjacent to the second trench, the third trench including a third shield electrode coupled to the source pad.

9. The semiconductor device of claim 1, further comprising:

a gate riser formed on the gate electrode and electrically coupled to the gate pad; and

a third trench disposed under the gate riser.

10. The semiconductor device of claim 1, further comprising:

a well region of a first conductivity type disposed in the epitaxial layer and adjacent to the first trench.

11. The semiconductor device of claim 10, wherein the well region is electrically floating.

12. The semiconductor device of claim 10, wherein the well region is electrically coupled to the source pad.

13. The semiconductor device of claim 1, further comprising:

a first well region disposed on a first side of the first trench, the first well region being electrically coupled to the source pad; and

a second well region disposed on a second side of the first trench, the second well being electrically floating.

14. The semiconductor device of claim 1, further comprising:

a first mesa of semiconductor material adjacent to the first trench;

a third trench disposed directly under the gate pad and adjacent to the second trench; and

a second mesa of semiconductor material disposed between the second trench and the third trench, the second mesa has a width that is approximately 1.25 times the width of the first mesa.

15. A semiconductor device, comprising:

a first trench extending into an epitaxial layer and including a first shield electrode and a gate electrode disposed therein, the first shield electrode of the first trench being electrically insulated from the gate electrode;

a gate riser electrically coupled to the gate electrode of the first trench;

a gate pad electrically coupled to the gate electrode of the first trench via the gate riser; and

a second trench extending into the epitaxial layer and having at least a portion disposed directly under the gate pad between the gate pad and a substrate, the second trench including a second shield electrode disposed therein, the second shield electrode having a vertical length greater than a vertical length of the first shield electrode.

16. The semiconductor device of claim 15, further comprising:

a source pad electrically coupled to the first shield electrode of the first trench.

17. The semiconductor device of claim 15, further comprising:

a source pad electrically coupled to the first shield electrode of the first trench and electrically coupled to the second shield electrode of the second trench.

18. The semiconductor device of claim 15, wherein the first shield electrode is electrically floating.

19. The semiconductor device of claim 15, wherein the second shield electrode is electrically floating.

20. The semiconductor device of claim 15, wherein the first trench is disposed directly below the gate riser.

21. The semiconductor device of claim 15, further comprising:

a third trench including a third shield electrode disposed therein, the first trench is disposed directly below the gate riser, the first trench is disposed between the second trench and the third trench.

22. The semiconductor device of claim 15, further comprising:

a third trench including an electrically floating electrode disposed therein, the first trench is disposed directly below the gate riser, the first trench is disposed between the second trench and the third trench.

23. The semiconductor device of claim 15, further comprising:

a first mesa of semiconductor material adjacent to the first trench;

a third trench disposed directly under the gate pad and adjacent to the second trench; and

a second mesa of semiconductor material disposed between the second trench and the third trench, the second mesa has a width that is approximately 1.25 times the width of the first mesa.

24. The semiconductor device of claim 15, wherein the second shield electrode of the second trench is electrically coupled to a source pad,

the semiconductor device further comprising:

a third trench including an electrically floating electrode disposed therein.

25. The semiconductor device of claim 15, further comprising:

a third trench disposed directly under the gate pad and adjacent to the second trench; and

a mesa of semiconductor material disposed between the second trench and the third trench and being an electrically floating mesa.

26. The semiconductor device of claim 15, further comprising:

a well region of a first conductivity type disposed in the epitaxial layer and adjacent to the first trench.

27. The semiconductor device of claim 26, wherein the well region is electrically floating.

28. The semiconductor device of claim 26, wherein the well region is electrically coupled to the source pad.