Electromigration immune through-substrate vias

• US 8,304,863 B2
• Filed: 02/09/2010
• Issued: 11/06/2012
• Est. Priority Date: 02/09/2010
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Filippi, Ronald G., Fitzsimmons, John A., Kolvenbach, Kevin, Wang, Ping-Chuan
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US12/702,463
• Publication Number:
  US 20110193199A1
• Time in Patent Office: 1,001 Days
• Field of Search: 438/629, 438637-639, 438/653
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]

Abstract

A through-substrate via (TSV) structure includes at least two electrically conductive via segments embedded in a substrate and separated from each other by an electrically conductive barrier layer therebetween. The length of each individual conductive via segment is typically equal to, or less than, the Blech length of the conductive material so that the stress-induced back flow force, generated by each conductive barrier layer, cancels the electromigration force in each conductive via segment. Consequently, the TSV structures are immune to electromigration, and provide reliable electrical connections among a chips stacked in 3 dimensions.

Claims

1. A semiconductor structure comprising:

a first substrate, said first substrate including at least one through-substrate via (TSV) structure extending from a first surface located on one side of said first substrate to a second surface located on an opposite side of said first substrate, each of said at least one TSV structure comprising a plurality of conductive via segments that are vertically spaced from one another by at least one conductive liner portion; and

an array of conductive bonding material structures located on said second surface of said first substrate, wherein each of said array of conductive bonding material structures contacts a bottom surface of a TSV structure within said at least one TSV structure, wherein each vertically adjacent pair of said plurality of conductive via segments is spaced from each other by a conductive liner portion among said at least one conductive liner portion, wherein a bottom surface of one of said vertically adjacent pair of conductive via segments is in contact with an upper surface of said conductive liner portion and a top surface of the other of said vertically adjacent pair of conductive via segments is in contact with a lower surface of said conductive liner portion, and wherein said lower surface of said conductive liner portion is in contact with another conductive liner portion that laterally surrounds, and contacts sidewalls of, said other of said vertically adjacent pair of conductive via segments.

2. The semiconductor structure of claim 1, wherein said at least one TSV structure is an array of TSV structures.

3. The semiconductor structure of claim 1, wherein said conductive liner portion extends upward from a periphery of said upper surface and laterally surrounds, and contacts sidewalls of, said one of said vertically adjacent pair of conductive via segments.

4. The semiconductor structure of claim 1, wherein each conductive via segment within one of said at least one TSV structure has a vertical length that is less than Blech length thereof for a maximum current density that said one of said at least one TSV structure is configured to flow within said first substrate in a vertical direction between said first surface and said second surface.

5. The semiconductor structure of claim 2, wherein said array of conductive bonding material structures is an array of C4 balls or an array of conductive bonding pads.

6. The semiconductor structure of claim 2, further comprising a second substrate bonded to said first substrate through said array of conductive bonding material, wherein said array of TSV structures and said array of conductive bonding material structures provide a plurality of electrical connections between at least one semiconductor device on said first surface of said first substrate and conductive structures located within said second substrate.

7. The semiconductor structure of claim 2, further comprising a packaging substrate bonded to said first substrate through said array of conductive bonding material, wherein said array of TSV structures and said array of conductive bonding material structures provide a plurality of electrical connections between at least one semiconductor device located on said first surface of said first substrate and conductive structures located within said packaging substrate.

8. The semiconductor structure of claim 6, wherein said second substrate includes at least another through-substrate via (TSV) structure extending from a third surface located on one side of said second substrate to a fourth surface located on an opposite side of said third surface, each of said at least another TSV structure comprising another plurality of conductive via segments that are vertically spaced from one another by at least another conductive liner portion.