Integrated circuit packaging system with stacked lead and method of manufacture thereof

• US 8,304,900 B2
• Filed: 08/11/2010
• Issued: 11/06/2012
• Est. Priority Date: 08/11/2010
• Status: Active Grant

• Current Assignee: Stats Chippac Pte. Ltd. (JCET Group Co., Ltd.)
• Original Assignee: Stats Chippac BVI limited (JCET Group Co., Ltd.)
• Inventors: Jang, Ki Youn, Kim, YoungJoon, Bae, JoHyun
• Primary Examiner(s): Louie, Wai Sing
• Application Number:
  US12/854,306
• Publication Number:
  US 20120038040A1
• Time in Patent Office: 818 Days
• Field of Search: 257/733, 257/775, 257/779, 257/780
• US Class Current: 257/733
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit device to the substrate; forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity.

Claims

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

attaching an integrated circuit device to the substrate;

forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate;

applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and

forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity.

2. The method as claimed in claim 1 wherein forming the cavity includes forming the cavity with a non-vertical side of the encapsulation.

3. The method as claimed in claim 1 wherein forming the stud interconnect includes forming a stud base of the stud interconnect on the substrate.

4. The method as claimed in claim 1 further comprising connecting another integrated circuit package to the crown surface.

5. The method as claimed in claim 1 further comprising attaching a package connector to a side of the substrate facing away from the encapsulation.

6. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

attaching an integrated circuit device to the substrate;

forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate;

applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate;

forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity; and

connecting a package connector to a side of the substrate opposite the encapsulation.

7. The method as claimed in claim 6 wherein forming the cavity in the encapsulation includes forming the cavity having an upper width greater than a lower width.

8. The method as claimed in claim 6 wherein forming the stud interconnect includes attaching the stud interconnect to a substrate conductor of the substrate.

9. The method as claimed in claim 6 further comprising connecting an integrated circuit package to the contact surface.

10. The method as claimed in claim 6 wherein connecting the package connector includes attaching the package connector to a substrate conductor on a side of the substrate opposite the encapsulation.

11. An integrated circuit packaging system comprising:

a substrate;

an integrated circuit device attached to the substrate;

a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; and

an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate, and the encapsulation having a cavity over the stud interconnect with the contact surface and the crown surface exposed in the cavity.

12. The system as claimed in claim 11 wherein the cavity includes the cavity formed with a non-vertical side of the encapsulation.

13. The system as claimed in claim 11 wherein the stud interconnect includes a stud base of the stud interconnect formed on the substrate.

14. The system as claimed in claim 11 further comprising another integrated circuit package connected to the crown surface.

15. The system as claimed in claim 11 further comprising a package connector connected to a side of the substrate facing away from the encapsulation.

16. The system as claimed in claim 11 further comprising a package connector connected to a side of the substrate opposite the encapsulation.

17. The system as claimed in claim 16 wherein the cavity includes having an upper width greater than a lower width.

18. The system as claimed in claim 16 wherein the stud interconnect includes the stud interconnect attached to a substrate conductor of the substrate.

19. The system as claimed in claim 16 further comprising an integrated circuit package connected to the contact surface.

20. The system as claimed in claim 16 wherein the package connector includes the package connector attached to a substrate conductor on a side of the substrate exposed from the encapsulation.