Logic circuit, light emitting device, semiconductor device, and electronic device

• US 8,305,109 B2
• Filed: 09/13/2010
• Issued: 11/06/2012
• Est. Priority Date: 09/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Okazaki, Kenichi, Oikawa, Yoshiaki, Maruyama, Hotaka, Godo, Hiromichi, Yamazaki, Shunpei
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US12/880,312
• Publication Number:
  US 20110062992A1
• Time in Patent Office: 785 Days
• Field of Search: 326/25, 326/102, 326112-113, 257/205, 257/392
• US Class Current: 326/25
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1233 with different thicknesses of the active layer in different devices
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

An object is to obtain a desired threshold voltage of a thin film transistor using an oxide semiconductor. Another object is to suppress a change of the threshold voltage over time. Specifically, an object is to apply the thin film transistor to a logic circuit formed using a transistor having a desired threshold voltage. In order to achieve the above object, thin film transistors including oxide semiconductor layers with different thicknesses may be formed over the same substrate, and the thin film transistors whose threshold voltages are controlled by the thicknesses of the oxide semiconductor layers may be used to form a logic circuit. In addition, by using an oxide semiconductor film in contact with an oxide insulating film formed after dehydration or dehydrogenation treatment, a change in threshold voltage over time is suppressed and the reliability of a logic circuit can be improved.

Claims

1. A logic circuit comprising:

a depletion-type transistor in which a high power supply potential is applied to one of a source and a drain and a gate is connected to the other of the source and the drain; and

an enhancement-type transistor in which one of a source and a drain is connected to the gate of the depletion-type transistor and a low power supply potential is applied to the other of the source and the drain,

wherein the depletion-type transistor and the enhancement-type transistor each comprise;

a first gate electrode;

a gate insulating film over the first gate electrode;

an oxide semiconductor layer over the gate insulating film;

a source electrode and a drain electrode which overlap with edge portions of the first gate electrode and which are in contact with the oxide semiconductor layer;

an oxide insulating film in contact with the oxide semiconductor layer and over a channel formation region; and

a protective insulating layer in contact with the oxide insulating film and over the oxide insulating film,

wherein a thickness of the oxide semiconductor layer of the depletion-type transistor is larger than a thickness of the oxide semiconductor layer of the enhancement-type transistor,

wherein a first signal is input to the first gate electrode of the enhancement-type transistor,

wherein a potential of a portion where the enhancement-type transistor and the depletion-type transistor are connected to each other is output as a second signal, and

wherein one of the depletion-type transistor and the enhancement-type transistor comprises a second gate electrode.

2. A logic circuit comprising:

a first transistor in which a first clock signal is input to a gate and an input signal is input to one of a source and a drain;

a first inverter circuit whose input terminal is electrically connected to the other of the source and the drain of the first transistor;

a second inverter circuit whose input terminal is electrically connected to an output terminal of the first inverter circuit;

a third inverter circuit whose input terminal is electrically connected to the output terminal of the first inverter circuit and which outputs an output signal from an output terminal; and

a second transistor in which a second clock signal is input to a gate, one of a source and a drain is electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain is electrically connected to an output terminal of the second inverter circuit,

wherein the first inverter circuit and the second inverter circuit include the logic circuit according to claim 1.

3. The logic circuit according to claim 1 or 2, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

4. The logic circuit according to claim 1,

wherein the oxide semiconductor layer of the depletion-type transistor includes a first layer and a second layer on the first layer, and

wherein the oxide semiconductor layer of the enhancement-type transistor is a single layer.

5. The logic circuit according to claim 4, wherein a thickness of the second layer of the depletion-type transistor is the same as a thickness of the oxide semiconductor layer of the enhancement-type transistor.

6. The logic circuit according to claim 1, wherein the source electrode or the drain electrode is connected to the first gate electrode through a contact hole in the gate insulating film in the depletion-type transistor.

14. A light emitting device comprising the logic circuit according to any one of claims 1, 2, 7, and 8.

15. A light emitting device comprising the logic circuit according to claim 14, wherein the light emitting device is a lighting device.

16. A semiconductor device comprising the logic circuit according to any one of claims 1, 2, 7, and 8.

17. An electronic device comprising the logic circuit according to any one of claims 1, 2, 7, and 8.

7. A logic circuit comprising:

a depletion-type transistor in which a high power supply potential is applied to one of a source and a drain and a gate is connected to the other of the source and the drain; and

an enhancement-type transistor in which one of a source and a drain is connected to the gate of the depletion-type transistor and a low power supply potential is applied to the other of the source and the drain,

wherein the depletion-type transistor and the enhancement-type transistor each comprise;

a gate electrode;

a gate insulating film over the gate electrode;

a source electrode and a drain electrode which overlap with edge portions of the gate electrode and which are provided over the gate insulating film;

an oxide semiconductor layer over the gate electrode, the oxide semiconductor layer being over and covering edge portions of the source electrode and the drain electrode;

an oxide insulating film in contact with the oxide semiconductor layer and over a channel formation region; and

a protective insulating layer in contact with the oxide insulating film and over the oxide insulating film,

wherein a thickness of the oxide semiconductor layer of the depletion-type transistor is larger than a thickness of the oxide semiconductor layer of the enhancement-type transistor,

wherein a first signal is input to the gate electrode of the enhancement-type transistor, and

wherein a potential of a portion where the enhancement-type transistor and the depletion-type transistor are connected to each other is output as a second signal.

8. A logic circuit comprising:

a first transistor in which a first clock signal is input to a gate and an input signal is input to one of a source and a drain;

a first inverter circuit whose input terminal is electrically connected to the other of the source and the drain of the first transistor;

a second inverter circuit whose input terminal is electrically connected to an output terminal of the first inverter circuit;

a third inverter circuit whose input terminal is electrically connected to the output terminal of the first inverter circuit and which outputs an output signal from an output terminal; and

a second transistor in which a second clock signal is input to a gate, one of a source and a drain is electrically connected to the other of the source and the drain of the first transistor, and the other of the source and the drain is electrically connected to an output terminal of the second inverter circuit,

wherein the first inverter circuit and the second inverter circuit include the logic circuit according to claim 7.

9. The logic circuit according to claim 7 or 8, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

10. The logic circuit according to claim 7,

wherein one of the depletion-type transistor and the enhancement-type transistor comprises a second gate electrode.

11. The logic circuit according to claim 7,

wherein the oxide semiconductor layer of the depletion-type transistor includes a first layer and a second layer on the first layer, and

wherein the oxide semiconductor layer of the enhancement-type transistor is a single layer.

12. The logic circuit according to claim 11, wherein a thickness of the second layer of the depletion-type transistor is the same as a thickness of the oxide semiconductor layer of the enhancement-type transistor.

13. The logic circuit according to claim 7, wherein the source electrode or the drain electrode is connected to the gate electrode through a contact hole in the gate insulating film in the depletion-type transistor.

18. A logic circuit comprising:

a first transistor in which a high power supply potential is applied to one of a source and a drain and a gate is connected to the other of the source and the drain; and

a second transistor in which one of a source and a drain is connected to the gate of the first transistor and a low power supply potential is applied to the other of the source and the drain,

wherein the first transistor and the second transistor each comprise;

a first gate electrode;

a gate insulating film over the first gate electrode;

an oxide semiconductor layer over the gate insulating film;

a source electrode and a drain electrode which overlap with edge portions of the first gate electrode and which are in contact with the oxide semiconductor layer;

an oxide insulating film in contact with the oxide semiconductor layer and over a channel formation region; and

a protective insulating layer in contact with the oxide insulating film and over the oxide insulating film,

wherein a thickness of the oxide semiconductor layer of the first transistor is larger than a thickness of the oxide semiconductor layer of the second transistor,

wherein a first signal is input to the first gate electrode of the second transistor,

wherein a potential of a portion where the second transistor and the first transistor are connected to each other is output as a second signal, and

wherein one of the first transistor and the second transistor comprises a second gate electrode.

19. The logic circuit according to claim 18, wherein the first transistor is a depletion-type transistor and the second transistor is an enhancement-type transistor.

20. The logic circuit according to claim 18, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

21. A logic circuit comprising:

a first transistor in which a high power supply potential is applied to one of a source and a drain and a gate is connected to the other of the source and the drain; and

a second transistor in which one of a source and a drain is connected to the gate of the first transistor and a low power supply potential is applied to the other of the source and the drain,

wherein the first transistor and the second transistor each comprise;

a gate electrode;

a gate insulating film over the gate electrode;

a source electrode and a drain electrode which overlap with edge portions of the gate electrode and which are provided over the gate insulating film;

an oxide semiconductor layer over the gate electrode, the oxide semiconductor layer being over and covering edge portions of the source electrode and the drain electrode;

an oxide insulating film in contact with the oxide semiconductor layer and over a channel formation region; and

a protective insulating layer in contact with the oxide insulating film and over the oxide insulating film,

wherein a thickness of the oxide semiconductor layer of the first transistor is larger than a thickness of the oxide semiconductor layer of the second transistor,

wherein a first signal is input to the gate electrode of the second transistor, and

wherein a potential of a portion where the second transistor and the first transistor are connected to each other is output as a second signal.

22. The logic circuit according to claim 21, wherein the first transistor is a depletion-type transistor and the second transistor is an enhancement-type transistor.

23. The logic circuit according to claim 21, wherein the oxide semiconductor layer comprises indium, gallium, and zinc.

24. The logic circuit according to claim 21,

wherein one of the first transistor and the second transistor comprises a second gate electrode.