Methods and apparatuses for high power and/or high frequency devices

• US 8,305,139 B1
• Filed: 10/05/2011
• Issued: 11/06/2012
• Est. Priority Date: 10/05/2011
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Dykstra, Jeffrey A.
• Primary Examiner(s): NGUYEN, PATRICIA T
• Application Number:
  US13/253,832
• Time in Patent Office: 398 Days
• Field of Search: 330/51, 330/311, 330/302, 327/359, 327/157, 455/326
• US Class Current: 330/51
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/534 Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/541 Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2203/45702 the LC comprising two resistors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45237 Complementary long tailed pairs having parallel inputs and being supplied in series

Abstract

Driver circuits and methods related thereto for driving high power and/or high frequency devices are described. The driver circuits comprise transistor stacks and capacitors coupled with the transistor stacks. Voltages across the capacitors depend on state (on or off) of each transistor in the transistor stacks. These voltages in turn determine output voltages generated by the driver circuits.

Claims

1. A circuital arrangement adapted to provide a first output voltage to a first output terminal and a second output voltage to a second output terminal, comprising:

a first transistor configured to receive a first control voltage;

a second transistor configured to receive a second control voltage;

a first capacitor connected with the first transistor on one end and the second transistor on another end;

a third transistor configured to receive the second control voltage;

a fourth transistor configured to receive the first control voltage; and

a second capacitor connected with the third transistor on one end and the fourth transistor on another end,

wherein;

the first capacitor is configured to store charge when the first transistor is switched on and is configured to couple a first capacitor voltage to the first output terminal when the first transistor is switched off, wherein the first and second output voltages are functions of the first capacitor voltage when the first transistor is switched off, and

the second capacitor is configured to store charge when the third transistor is switched on and is configured to couple a second capacitor voltage to the second output terminal when the third transistor is switched off, wherein the first and second output voltages are functions of the second capacitor voltage when the third transistor is switched off.

2. The circuital arrangement according to claim 1, wherein:

each of the first and second control voltages comprises a first state and a second state,

when the first control voltage is in the first state, the third and fourth transistors are switched on, and

when the first control voltage is in the second state, the first and second transistors are switched on.

3. The circuital arrangement according to claim 1, further comprising:

a fifth transistor connected with the first capacitor and configured to receive the second control voltage;

a sixth transistor connected with the first capacitor and configured to receive the first control voltage;

a seventh transistor connected with the second capacitor and configured to receive the first control voltage; and

an eighth transistor connected with the second capacitor and configured to receive the second control voltage,

wherein;

the first capacitor voltage is to be applied to the fifth and sixth transistors and is suitable for switching on the fifth and sixth transistors, and

the second capacitor voltage is to be applied to the seventh and eighth transistors and is suitable for switching on the seventh and eighth transistors.

4. The circuital arrangement according to claim 3, wherein:

each of the first and second control voltages comprises a first state and a second state,

when the first control voltage is in the first state, the third and fourth transistors are switched on, and

when the first control voltage is in the second state, the first and second transistors are switched on.

5. The circuital arrangement according to claim 4, wherein:

when the first control voltage is in the first state, the fifth transistor is switched on and configured to couple one end of the first capacitor to the first output terminal and the sixth transistor is switched on and configured to couple another end of the first capacitor to the second output terminal, and

when the first control voltage is in the second state, the seventh transistor is switched on and configured to couple one end of the second capacitor to the second output terminal and the eighth transistor is switched on and configured to couple another end of the second capacitor to the first output terminal.

6. The circuital arrangement according to claim 1, further comprising:

a third capacitor coupled with the first capacitor, second capacitor, and first output terminal; and

a fourth capacitor coupled with the first capacitor, second capacitor, and the second output terminal.

7. The circuital arrangement according to claim 1, wherein each of the first, second, third, and fourth transistors is either a field effect transistor or a bipolar junction transistor.

8. The circuital arrangement according to claim 1, wherein at least one of the first, second, third, and fourth transistors is serially connected with one or more serially-connected transistors.

9. The circuital arrangement according to claim 1, wherein the first control voltage is complementary to the second control voltage.

10. A mixer circuit adapted to generate an output signal based on a first input signal and a second input signal, comprising:

a plurality of drivers, wherein an input to each driver is a function of the first input signal, and wherein each driver in the plurality of drivers is the circuital arrangement according to claim 1; and

a bridge circuit connected with the plurality of drivers, wherein;

the bridge circuit comprises a plurality of transistors, and

the bridge circuit is adapted to receive the second input signal and is adapted to generate the output signal;

wherein an output of each driver in the plurality of drivers controls state of each transistor in the plurality of transistors and each transistor is either in an on state or an off state.

11. The mixer circuit according to claim 10, wherein the output signal is of lower frequency than the first input signal and the second input signal.

12. The mixer circuit according to claim 10, wherein the bridge circuit comprises a plurality of transistor stacks, each transistor stack comprising one transistor or one or more serially-connected transistors.

13. An amplifier circuit adapted to generate an output signal based on an input signal, comprising:

a plurality of drivers, wherein an input to each driver is a function of the input signal, and wherein each driver in the plurality of drivers is the circuital arrangement according to claim 1; and

a plurality of transistor stacks connected with the plurality of drivers and adapted to generate the output signal,

wherein an output of each driver in the plurality of drivers controls state of each transistor in the plurality of transistor stacks and each transistor is either in an on state or an off state.

14. A switching circuit adapted to receive a first input signal and a second input signal and either transmit the second input signal to an output terminal or ground the second input signal, comprising:

a plurality of drivers, wherein an input to each driver is a function of the first input signal, and wherein each driver in the plurality of drivers is the circuital arrangement according to claim 1;

a first transistor configured to receive the second input signal; and

a second transistor coupled with the first transistor,

wherein;

an output of each driver in the plurality of drivers controls state of each of the first and second transistor and each transistor is either in an on state or an off state,

when the first transistor is switched on, the switching circuit is configured to transmit the second input signal to the output terminal, and

when the second transistor is switched on, the switching circuit is configured to ground the second input signal.

15. A method for providing a first output voltage and a second output voltage to a receiving circuit, comprising:

providing a first transistor, a second transistor, a third transistor, and a fourth transistor;

providing a first capacitor connected with the first transistor on one end and the second transistor on another end;

providing a second capacitor connected with the third transistor on one end and the fourth transistor on another end;

applying a first control voltage to the first and fourth transistors, the first control voltage controlling state of the first and fourth transistors;

applying a second control voltage to the second and third transistors, the second control voltage controlling state of the second and third transistors;

generating the first output voltage based on voltage across the first capacitor; and

generating the second output voltage based on voltage across the second capacitor,

wherein the state of each transistor is either an on state or an off state.

16. The method according to claim 15, wherein:

the generating the first output voltage comprises;

charging the first capacitor when the first transistor is switched on, and

coupling the first capacitor to the receiving circuit when the first transistor is switched off, wherein the voltage across the first capacitor is based on the charging; and

the generating the second output voltage comprises;

charging the second capacitor when the third transistor is switched on, and

coupling the second capacitor to the receiving circuit when the first transistor is switched off, wherein the voltage across the second capacitor is based on the charging.

17. The method according to claim 15, wherein the first control voltage and the second control voltage are complementary voltages.

18. The method according to claim 15, wherein at least one of the provided first, second, third, and fourth transistors is serially connected with one or more serially-connected transistors.

19. The method according to claim 15, further comprising:

providing a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein;

the fifth transistor is connected with the first transistor and the first capacitor,

the sixth transistor is connected with the second transistor and the first capacitor,

the seventh transistor is connected with the third transistor and the second capacitor, and

the eighth transistor is connected with the fourth transistor and the second capacitor;

applying the first control voltage to the sixth and seventh transistors, the first control voltage controlling state of the sixth and seventh transistors;

applying the second control voltage to the fifth and eighth transistors, the second control voltage controlling state of the fifth and eighth transistors;

generating the first output voltage based on voltage across the first capacitor; and

generating the second output voltage based on voltage across the second capacitor,

wherein;

the state of each transistor is either an on state or an off state,

the first output voltage is further based on state of the fifth transistor and the eighth transistor, and

the second output voltage is further based on state of the sixth transistor and the seventh transistor.

20. The method according to claim 15, wherein the first control voltage is complementary to the second control voltage.