Liquid crystal display element and pixel structure
First Claim
1. A liquid crystal display element disposed in a pixel area including a first sub-pixel area, a second sub-pixel area, a third sub-pixel area and a fourth sub-pixel area arranged in an array, comprising:
- a first pixel element, comprising;
a first sub-pixel electrode and a second sub-pixel electrode disposed in the first sub-pixel area and the second sub-pixel area respectively, wherein the first sub-pixel electrode is adjacent to the second sub-pixel electrode and each of the first sub-pixel electrode and the second sub-pixel electrode comprises at least two display domains at the left and the right; and
a first transistor and a second transistor, wherein the first sub-pixel electrode and the second sub-pixel electrode are respectively connected to the first transistor and the second transistor;
a second pixel element, comprising;
a third sub-pixel electrode and a fourth sub-pixel electrode disposed in the third sub-pixel area and the fourth sub-pixel area respectively, wherein the third sub-pixel electrode is adjacent to the fourth sub-pixel electrode and the third sub-pixel electrode and the fourth sub-pixel electrode respectively at least comprises two display domains at the left and the right; and
a third transistor and a fourth transistor, wherein the fourth sub-pixel electrode and the third sub-pixel electrode are respectively connected to the third transistor and the fourth transistor;
a first pair of data lines, including a first data line and a second data line, wherein the first data line is disposed at an interface between the at least two display domains of the first sub-pixel electrode and at an interface between the at least two display domains of the second sub-pixel electrode, and the second data line is disposed at edges of the first pixel element;
a second pair of data lines, including a third data line and a fourth data line, wherein the third data line is disposed at an interface between the at least two display domains of the third sub-pixel electrode and at an interface between the at least two display domains of the fourth sub-pixel electrode, and the fourth data line is disposed at edges of the second pixel element; and
a gate line disposed between the first sub-pixel electrode and the second sub-pixel electrode, and disposed between the third sub-pixel electrode and the fourth sub-pixel electrode, wherein the first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode and the fourth sub-pixel electrode are respectively controlled by the first data line, the second data line, the fourth data line and the third data line through the first transistor, the second transistor, the fourth transistor and the third transistor;
wherein the first sub-pixel electrode and the second sub-pixel electrode in the first pixel element are respectively driven by a first voltage provided by the first data line and a second voltage provided by the second data line, and the third sub-pixel electrode and the fourth sub-pixel electrode in the second pixel element are respectively driven by a fourth voltage provided by the fourth data line and a third voltage provided by the third data line,wherein the first voltage and the second voltage have opposite polarities, and the third voltage and the fourth voltage have opposite polarities,wherein the first sub-pixel electrode and the second sub-pixel electrode are inputted voltages of opposite polarities, and the third sub-pixel electrode and the fourth sub-pixel electrode are inputted voltages of opposite polarities; and
wherein each of the first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode and the fourth sub-pixel electrode is coupled with two data lines having opposite polarities.
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Accused Products
Abstract
A pixel structure of liquid crystal display including a first and a second sub-pixel electrodes, a first and a second data lines, a gate line, and a first and a second transistors is provided. The first and the second sub-pixel electrodes disposed in the first and second sub-pixel areas respectively include at least two display domains at left and right. The first data line is disposed under the interface between two domains of each of the first and second sub-pixel electrodes, and the second data line is disposed under the edges of the first and second sub-pixel electrodes. The gate line is disposed between the first and second sub-pixel areas. The first sub-pixel electrode is controlled by the gate line and the first data line through the first transistor. The second sub-pixel electrode is controlled by the gate line and the second data line through the second transistor.
12 Citations
14 Claims
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1. A liquid crystal display element disposed in a pixel area including a first sub-pixel area, a second sub-pixel area, a third sub-pixel area and a fourth sub-pixel area arranged in an array, comprising:
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a first pixel element, comprising; a first sub-pixel electrode and a second sub-pixel electrode disposed in the first sub-pixel area and the second sub-pixel area respectively, wherein the first sub-pixel electrode is adjacent to the second sub-pixel electrode and each of the first sub-pixel electrode and the second sub-pixel electrode comprises at least two display domains at the left and the right; and a first transistor and a second transistor, wherein the first sub-pixel electrode and the second sub-pixel electrode are respectively connected to the first transistor and the second transistor; a second pixel element, comprising; a third sub-pixel electrode and a fourth sub-pixel electrode disposed in the third sub-pixel area and the fourth sub-pixel area respectively, wherein the third sub-pixel electrode is adjacent to the fourth sub-pixel electrode and the third sub-pixel electrode and the fourth sub-pixel electrode respectively at least comprises two display domains at the left and the right; and a third transistor and a fourth transistor, wherein the fourth sub-pixel electrode and the third sub-pixel electrode are respectively connected to the third transistor and the fourth transistor; a first pair of data lines, including a first data line and a second data line, wherein the first data line is disposed at an interface between the at least two display domains of the first sub-pixel electrode and at an interface between the at least two display domains of the second sub-pixel electrode, and the second data line is disposed at edges of the first pixel element; a second pair of data lines, including a third data line and a fourth data line, wherein the third data line is disposed at an interface between the at least two display domains of the third sub-pixel electrode and at an interface between the at least two display domains of the fourth sub-pixel electrode, and the fourth data line is disposed at edges of the second pixel element; and a gate line disposed between the first sub-pixel electrode and the second sub-pixel electrode, and disposed between the third sub-pixel electrode and the fourth sub-pixel electrode, wherein the first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode and the fourth sub-pixel electrode are respectively controlled by the first data line, the second data line, the fourth data line and the third data line through the first transistor, the second transistor, the fourth transistor and the third transistor; wherein the first sub-pixel electrode and the second sub-pixel electrode in the first pixel element are respectively driven by a first voltage provided by the first data line and a second voltage provided by the second data line, and the third sub-pixel electrode and the fourth sub-pixel electrode in the second pixel element are respectively driven by a fourth voltage provided by the fourth data line and a third voltage provided by the third data line, wherein the first voltage and the second voltage have opposite polarities, and the third voltage and the fourth voltage have opposite polarities, wherein the first sub-pixel electrode and the second sub-pixel electrode are inputted voltages of opposite polarities, and the third sub-pixel electrode and the fourth sub-pixel electrode are inputted voltages of opposite polarities; and wherein each of the first sub-pixel electrode, the second sub-pixel electrode, the third sub-pixel electrode and the fourth sub-pixel electrode is coupled with two data lines having opposite polarities. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification