Common drain non-volatile multiple-time programmable memory

• US 8,305,805 B2
• Filed: 12/02/2009
• Issued: 11/06/2012
• Est. Priority Date: 11/03/2008
• Status: Expired due to Fees

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Liu, David K. Y.
• Primary Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US12/629,754
• Publication Number:
  US 20100109066A1
• Time in Patent Office: 1,070 Days
• Field of Search: 365/185.03, 365/185.24
• US Class Current: 365/185.03
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

An array of programmable non-volatile devices use a floating gate that functions as a FET gate that overlaps a portion of a common source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A programmable non-volatile device situated on a substrate, the programmable non-volatile device comprising:

a floating gate, wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with at least one of a logic gate or a volatile memory;

a common drain region which is shared in common with at least one additional programmable non-volatile device;

a source region; and

an n-type channel coupling said source region and said common drain region;

wherein the common drain region overlaps a sufficient portion of said floating gate to areally capacitively couple the common drain region to the floating gate such that a programming voltage for the device applied across said common drain region and said source region can be imparted to said floating gate through the areal capacitive coupling from said common drain region to said floating gate.

2. The programmable device of claim 1 wherein said common drain region is shared by four (4) programmable non-volatile devices.

3. The programmable device of claim 1 wherein said floating gate is programmed by a voltage applied to said source region.

4. The programmable device of claim 1 wherein a state of said floating gate can be determined by a read signal applied to said source.

5. The programmable device of claim 1 wherein said device is part of a programmable array embedded with at least one of separate logic circuits or memory circuits in an integrated circuit.

6. The programmable device of claim 5 wherein said device is associated with at least one of a data encryption circuit;

a reference trimming circuit;

a manufacturing ID;

or a security ID.

7. A programmable device situated on a substrate, the programmable device comprising:

a floating gate;

said floating gate being comprised of a material that includes impurities acting as charge storage sites and is also used as an insulating layer for other non-programmable devices situated on the substrate;

a source region;

a common drain region which is shared in common with at least one additional programmable non-volatile device; and

an n-type channel coupling said source region and common drain region;

wherein the common drain region overlaps a sufficient portion of said floating gate such that a programming voltage applied across said common drain region and source region can be imparted to said floating gate through capacitive coupling from said common drain region to said floating gate.

8. A one-time programmable (OTP) device situated on a substrate, the one-time programmable (OTP) device comprising:

a floating gate;

wherein said floating gate is comprised of a material that is also shared by at least one of an interconnect or another gate for a transistor device also situated on the substrate and associated with at least one of a logic gate or a volatile memory;

a source region;

a common drain region overlapping a portion of said floating gate and capacitively coupled thereto, and which common drain region is shared in common with at least one additional OTP device; and

an n-type channel coupling said source region and common drain region;

wherein a threshold of said floating gate can be permanently altered by applying a programming voltage across said common drain region and said source region to cause injection of channel hot electrons to store data in the OTP device.

9. A one-time programmable (OTP) memory device incorporated on a silicon substrate with at least one other additional logic device or non-OTP memory device, characterized in that:

a. said OTP memory device has an n-type channel, a common drain region shared with other OTP memory devices, and a floating gate, wherein the common drain region overlaps a sufficient portion of said floating gate such that a programming voltage can be imparted to said floating gate through capacitive coupling from said common drain region to said floating gate; and

b. any and all regions and structures of said OTP memory device are derived solely from corresponding regions and structures used as components of at least one of the additional logic device or non-OTP memory device.

10. A programmable memory device with a gate, an n-type impurity source and an n-type impurity common drain on a silicon substrate, the programmable memory device comprising:

an n-type channel;

wherein the n-type impurity common drain overlaps a sufficient portion of said gate such that a programming voltage applied to said n-type impurity drain can be imparted to said gate through capacitive coupling from said common drain to said gate;

wherein the n-type impurity common drain is shared in common with at least one additional programmable device;

said gate being adapted to function as a floating gate so that the device has a programmed state defined by an amount of charge stored on said gate by said programming voltage;

further wherein said charge on said floating gate can be erased so as to permit the device to be re-programmed.