Flash memory device and method of reading data

• US 8,305,811 B2
• Filed: 05/17/2010
• Issued: 11/06/2012
• Est. Priority Date: 06/19/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jeon, Su-chang
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US12/780,982
• Publication Number:
  US 20100322007A1
• Time in Patent Office: 904 Days
• Field of Search: 365/185.18, 365/185.12, 365/201
• US Class Current: 365/185.18
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A flash memory device and method of reading data are disclosed. The method includes; performing a test read operation directed to test data stored in a memory cell array of the flash memory device by iteratively applying a sequence of test read retry operations, wherein each successive test read retry operation uses a respectively higher test read voltage level than a preceding test read retry operation, until one test read retry operation in the sequence of test read retry operations successfully reads the test data using a minimum test read retry voltage associated with the one test read retry operation, setting an initial read voltage for the flash memory device equal to the minimum test read retry voltage, and thereafter performing a normal read operation directed to user data stored in the memory cell array by iteratively applying a sequence of read retry operations, wherein an initial read retry operation in the sequence of read retry operations uses the initial read voltage.

Claims

1. A method of reading data from a flash memory device, the method comprising:

performing a test read operation directed to test data stored in a memory cell array of the flash memory device by iteratively applying a sequence of test read retry operations, wherein each successive test read retry operation uses a respectively higher test read voltage level than a preceding test read retry operation, until one test read retry operation in the sequence of test read retry operations successfully reads the test data using a minimum test read retry voltage associated with the one test read retry operation;

setting an initial read voltage for the flash memory device equal to the minimum test read retry voltage; and

thereafter

performing a normal read operation directed to user data stored in the memory cell array by iteratively applying a sequence of read retry operations, wherein an initial read retry operation in the sequence of read retry operations uses the initial read voltage.

2. The method of claim 1, wherein performing the test read operation is begun upon receiving power to the flash memory device during a power-up operation.

3. The method of claim 2, further comprising:

reading set data stored in the flash memory device after the power-up operation and before performing the test read operation to identify a test address at which the test data is stored, and obtain read retry information defining a read retry start voltage, wherein an initial test read retry operation in the sequence of test read retry operations is performed using the read retry start voltage.

4. The method of claim 1, wherein the sequence of read retry operations in the normal read operation comprises the initial read retry operation through an Nth read retry operation, and

each read retry operation in sequence of read retry operations uses a respectively higher read voltage ranging from the initial read voltage having a lowest level to an Nth read voltage having a highest level.

5. The method of claim 4, wherein upon applying the Nth read retry operation and still failing to successfully read the user data, the method further comprises:

redefining the sequence of read retry operations to additionally include an N+1 read retry operation using a N+1 read voltage having a level higher than the highest level.

6. The method of claim 5, wherein upon redefining the sequence of read retry operations to additionally include the N+1 read retry operation, the method further comprises:

extending a time period within the flash memory device during which the normal read operation may be performed.

7. The method of claim 1, wherein the test read data is stored in a designated test block within the memory cell array of the flash memory device, and

the user data is stored in a user data region separately designated from the test block.

8. The method of claim 7, wherein the test data is stored in a designated test page within the test block.

9. The method of claim 8, wherein the test page is a first page in the test block, a last page in the test block, or an intermediate page between the first and last pages in the test block.

10. A flash memory device comprising:

a memory cell array comprising a set data region, a test block, and a user data region;

a controller configured to control the execution of a normal read operation directed to user data stored in the user data region, and execution of a test read operation directed to test data stored in the test block,

wherein execution of the normal read operation comprises iteratively applying a sequence of read retry operations, and

execution of the test read operation comprises iteratively applying a sequence of test read retry operations, such that each successive test read retry operation uses a respectively higher test read voltage level than a preceding test read retry operation, until one test read retry operation in the sequence of test read retry operations successfully reads the test data using a minimum test read retry voltage associated with the one test read retry operation; and

a read retry start voltage setting unit configured to store the minimum test read retry voltage as an initial read voltage;

wherein the sequence of read retry operations comprises the initial read retry operation through an Nth read retry operation, and each read retry operation in the sequence of read retry operations uses a respectively higher read voltage ranging from the initial read voltage having a lowest level to an Nth read voltage having a highest level.

11. The flash memory device of claim 10, wherein the controller is further configured to start the test read operation when power is supplied to the flash memory device during a power-up operation.

12. The flash memory device of claim 10, wherein the controller is further configured to read set data stored in the flash memory device, the set data indicating a test address at which the test data is stored, and read retry information defining a read retry start voltage, wherein an initial test read retry operation in the sequence of test read retry operations is performed using the read retry start voltage.

13. The flash memory device of claim 10, upon applying the Nth read retry operation and still failing to successfully read the user data during the normal read operation, the controller is further configured to redefine the sequence of read retry operations to additionally include an N+1 read retry operation using a N+1 read voltage having a level higher than the highest level.

14. The flash memory device of claim 13, wherein upon redefining the sequence of read retry operations to additionally include the N+1 read retry operation, the controller is further configured to extend a time period within the flash memory device during which the normal read operation may be performed.

15. The flash memory device of claim 10, wherein the test data is stored in the test block, and the user data is stored in the user data region separately designated from the test block.

16. The flash memory device of claim 15, wherein the test data is stored in a designated test page within the test block.

17. The flash memory device of claim 16, wherein the test page is a first page in the test block, a last page in the test block, or an intermediate page between the first and last pages in the test block.

18. A computational system comprising:

a central processing unit connected to a flash memory device via a system bus and configured to control execution of a normal read operation directed to user data stored in the flash memory device,

wherein the flash memory device comprises;

a memory cell array comprising a set data region, a test block, and a user data region;

a controller configured to control the execution of a normal read operation directed to user data stored in the user data region, and execution of a test read operation directed to test data stored in the test block,

wherein execution of the normal read operation comprises iteratively applying a sequence of read retry operations, and

execution of the test read operation comprises iteratively applying a sequence of test read retry operations, such that each successive test read retry operation uses a respectively higher test read voltage level than a preceding test read retry operation, until one test read retry operation in the sequence of test read retry operations successfully reads the test data using a minimum test read retry voltage associated with the one test read retry operation; and

a read retry start voltage setting unit configured to store the minimum test read retry voltage as an initial read voltage;

wherein the sequence of read retry operations comprises the initial read retry operation through an Nth read retry operation, and each read retry operation in the sequence of read retry operations uses a respectively higher read voltage ranging from the initial read voltage having a lowest level to an Nth read voltage having a highest level.