Data processing apparatus and method for use in a 0.5K mode interleaver in a digital video broadcasting standard including DVB-Terrestrial2
First Claim
1. A data processing apparatus operable to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising:
- an interleaver operable to read-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, andan address generator operable to generate the set of addresses, the addresses being generated for the input symbols to indicate the sub-carrier signals onto which the data symbols are to be mapped, the address generator comprising;
a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial,a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM sub-carriers, anda control unit operable in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, whereinthe predetermined maximum valid address is approximately five hundred, andthe linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of
R′
i[7]=R′
i-1[0]⊕
R′
i-1[1]⊕
R′
i-1[5]⊕
R′
i-1[6]and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage R′
i[n] in accordance with the table;
1 Assignment
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Accused Products
Abstract
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit.
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Citations
49 Claims
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1. A data processing apparatus operable to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising:
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an interleaver operable to read-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and an address generator operable to generate the set of addresses, the addresses being generated for the input symbols to indicate the sub-carrier signals onto which the data symbols are to be mapped, the address generator comprising; a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM sub-carriers, and a control unit operable in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately five hundred, and the linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of
R′
i[7]=R′
i-1[0]⊕
R′
i-1[1]⊕
R′
i-1[5]⊕
R′
i-1[6]and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage R′
i[n] in accordance with the table; - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A data processing apparatus operable to map symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream, the data processing apparatus comprising:
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a de-interleaver operable to read-into a memory the predetermined number of data symbols from the OFDM sub-carrier signals, and to read-out of the memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals, and an address generator operable to generate the set of addresses, the addresses being generated for the received data symbols to indicate the OFDM sub-carrier signals from which the received data symbols are to be mapped into the output symbol stream, the address generator comprising; a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM sub-carriers, and a control unit operable in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately five hundred, and the linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of R′
i[7]=R′
i-1[0]⊕
R′
i-1[1]⊕
R′
i-1[5]⊕
R′
i-1[6], and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage Ri[n] in accordance with the table; - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method of mapping input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the method comprising:
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reading-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, reading-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, and generating the set of addresses, the addresses being generated for the input symbols to indicate the sub-carrier signals onto which the data symbols are to be mapped, the generating the set of addresses comprising; using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial, using a permutation circuit operable to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation order to form an address, and re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately five hundred, and the linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of R′
i[7]=R′
i-1[0]⊕
R′
i-1[1]⊕
R′
i-1[5]⊕
R′
i-1[6], and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage R;
[n] in accordance with the table; - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A method of mapping symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream, the method comprising:
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reading-into a memory the predetermined number of data symbols from the OFDM sub-carrier signals, reading-out of the memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals, and generating the set of addresses, the addresses being generated for each of the received symbols to indicate the OFDM sub-carrier signals from which the received data symbols are to be mapped into the output symbol stream, the generating the set of addresses comprising; using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial, using a permutation circuit to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address, and re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately five hundred, and the linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of R′
i[7]=R′
i-1[0]⊕
R′
i-1[1]⊕
R′
i-1[5]⊕
R′
i-1[6], and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage R′
i[n] in accordance with the table; - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40)
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41. An address generator for use with transmission or reception of data symbols interleaved onto sub-carriers of an Orthogonal Frequency Division Multiplexed symbol, the address generator being operable to generate a set of addresses, the addresses being generated for the data symbols to indicate the sub-carrier signals onto which the data symbols are to be mapped, the address generator comprising:
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a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address, and a control unit operable in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately five hundred, and the linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of R′
i[7]=R′
i-1[0]⊕
R′
i-1[1]⊕
R′
i-1[5]⊕
R′
i-1[6], and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage R′
i[n] in accordance with the table;
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42. A transmitter for transmitting data using Orthogonal Frequency Division Multiplexing (OFDM), the transmitter including a data processing apparatus operable to map input data symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising:
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an interleaver operable to read-into an interleaver memory the predetermined number of input data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the interleaver memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, an address generator operable to generate the set of addresses, the addresses being generated for the input data symbols to indicate the sub-carrier signals onto which the data symbols are to be mapped, the address generator comprising; a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation code to form an address of one of the OFDM sub-carriers, and a control unit operable in combination with an address check circuit to regenerate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately five hundred, and the linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of R′
i-1[7]=R′
i-1[0]⊕
R′
i-1[1]⊕
R′
i-1[5]⊕
R′
i-1[6] and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage R′
i[n] in accordance with the table; - View Dependent Claims (43)
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44. A receiver for receiving data from Orthogonal Frequency Division Multiplexing (OFDM) modulated signal, the receiver including a data processing apparatus operable to map symbols received from a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol into an output symbol stream, the data processing apparatus comprising:
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a de-interleaver operable to read-into a memory the predetermined number of data symbols from the OFDM sub-carrier signals, and to read-out of the memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals, and an address generator operable to generate the set of addresses, the addresses being generated for the received data symbols to indicate the OFDM sub-carrier signal from which the received data symbols are to be mapped into the output symbol stream, the address generator comprising; a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial, a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM sub-carriers, and a control unit operable in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately five hundred, and the linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of R′
i-1[7]=R′
i-1[0]⊕
R′
i-1[1]⊕
R′
i-1[5]⊕
R′
i-1[6] and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage R′
i[n] in accordance with the table; - View Dependent Claims (45)
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46. A method of transmitting input data symbols via a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the method comprising:
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receiving a predetermined number of the input data symbols for mapping onto the predetermined number of sub-carrier signals, reading-into an interleaver memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, reading-out of the interleaver memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the input data symbols are interleaved on the sub-carrier signals, generating the set of addresses, the addresses being generated for the input data symbols to indicate the sub-carrier signals onto which the input data symbols are to be mapped, the generating the set of addresses comprising; using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with a generator polynomial, using a permutation circuit operable to receive the content of the shift register stages to permute the bits present in the register stages in accordance with a permutation code to form an address, and re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately five hundred, and the linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of R′
i[7]=R′
i-1[0]⊕
R′
i-1[1]⊕
R′
i-1[5]⊕
R′
i-1[6], and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage R′
i[n] in accordance with the table; - View Dependent Claims (47)
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48. A method of receiving data from Orthogonal Frequency Division Multiplexing OFDM modulated symbols, the method comprising:
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receiving a predetermined number of data symbols from a predetermined number of sub-carrier signals from the OFDM symbols for forming an output data stream, reading-into an interleaver memory the predetermined number of data symbols from the OFDM sub-carrier signals, reading-out of the interleaver memory the data symbols into the output symbol stream to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are de-interleaved from the OFDM sub-carrier signals, and generating the set of addresses, the addresses being generated for the received symbols to indicate the OFDM sub-carrier signals from which the received data symbols are to be mapped into the output symbol stream, the generating the set of addresses comprising; using a linear feedback shift register including a predetermined number of register stages to generate a pseudo-random bit sequence in accordance with generator polynomial, using a permutation circuit to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation code to form an address, and re-generating an address when a generated address exceeds a predetermined maximum valid address, wherein the predetermined maximum valid address is approximately five hundred, and the linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of R′
i[7]=R′
i-1[0]⊕
R′
i-1[5]⊕
R′
i-1[6], and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage R′
i[n] in accordance with the table; - View Dependent Claims (49)
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Specification