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Data processing apparatus and method for use in a 0.5K mode interleaver in a digital video broadcasting standard including DVB-Terrestrial2

  • US 8,306,137 B2
  • Filed: 10/24/2008
  • Issued: 11/06/2012
  • Est. Priority Date: 10/30/2007
  • Status: Active Grant
First Claim
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1. A data processing apparatus operable to map input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol, the data processing apparatus comprising:

  • an interleaver operable to read-into a memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals, andan address generator operable to generate the set of addresses, the addresses being generated for the input symbols to indicate the sub-carrier signals onto which the data symbols are to be mapped, the address generator comprising;

    a linear feedback shift register including a predetermined number of register stages and being operable to generate a pseudo-random bit sequence in accordance with a generator polynomial,a permutation circuit operable to receive the content of the shift register stages and to permute the bits present in the register stages in accordance with a permutation order to form an address of one of the OFDM sub-carriers, anda control unit operable in combination with an address check circuit to re-generate an address when a generated address exceeds a predetermined maximum valid address, whereinthe predetermined maximum valid address is approximately five hundred, andthe linear feedback shift register has eight register stages with a generator polynomial for the linear feedback shift register of
    R′

    i[7]=R′

    i-1[0]⊕

    R′

    i-1[1]⊕

    R′

    i-1[5]⊕

    R′

    i-1[6]and the permutation order forms, with an additional bit, a nine bit address Ri[n] for the i-th data symbol from the bit present in the n-th register stage R′

    i[n] in accordance with the table;

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