Synchronization circuit and synchronization method, wireless communication device and wireless communication method, and computer program

• US 8,306,160 B2
• Filed: 07/31/2009
• Issued: 11/06/2012
• Est. Priority Date: 09/09/2008
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Takahashi, Hiroaki, Takano, Hiroaki
• Primary Examiner(s): Nguyen, Leon-Viet
• Application Number:
  US12/533,582
• Publication Number:
  US 20100061493A1
• Time in Patent Office: 1,194 Days
• Field of Search: 370/208, 370/331, 370/503, 375/260, 375/340, 375/343, 375/354
• US Class Current: 375/343
• CPC Class Codes: H04L 2025/03414 Multicarrier
• CPC Class Codes: H04L 2025/03426 transmission using multiple-input and multiple-output channels
• CPC Class Codes: H04L 25/0204 of multiple channels
• CPC Class Codes: H04L 27/2655 Synchronisation arrangements
• CPC Class Codes: H04L 27/2675 Pilot or known symbols
• CPC Class Codes: H04L 5/0023 Time-frequency-space
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

A synchronizing circuit comprising: a coarse synchronizing circuit which determines temporary reception timing using a preamble consisting of a repetition of known training signals added to a reception packet; a synchronization candidate timing control section which sets up multiple synchronization candidates based on the temporary reception timing and controls synchronization of received signal s in each of the multiple synchronization candidates; a signal quality monitoring section which monitors signal quality of the received signal s synchronized in each of the multiple synchronization candidates; and a synchronization candidate selecting section which selects one of the synchronization candidates as a final reception timing based on a monitoring result of the signal quality in the signal quality monitoring section.

Claims

1. A synchronizing circuit comprising:

a coarse synchronizing circuit which determines temporary reception timing using a preamble consisting of repetitions of known training signals added to a received packet;

a synchronization candidate timing control section which sets up multiple synchronization candidates on the basis of the temporary reception timing and controls synchronization of received signals in each of the multiple synchronization candidates, a first, a second, and a third synchronization candidate from the multiple synchronization candidates set at the temporary reception timing minus a predetermined time period, at the temporary reception timing, and at the temporary reception timing plus the predetermined time period, respectively, the first, second, and third synchronization candidates processed at the same time;

a signal quality monitoring section which monitors signal quality of the received signals synchronized in each of the multiple synchronization candidates; and

a synchronization candidate selecting section which selects one of the synchronization candidates as final reception timing on the basis of a monitoring result of the signal quality in the signal quality monitoring section.

2. The synchronizing circuit according to claim 1, wherein the coarse synchronizing circuit determines temporary reception timing through autocorrelation of the preamble of the reception packet.

3. The synchronizing circuit according to claim 1, wherein the synchronization candidate selecting section selects a synchronization candidate with the best quality as final reception timing on the basis of predetermined selection criteria.

4. The synchronizing circuit according to claim 1 applied to a receiver with multiple reception branches, wherein:

the synchronization candidate timing control section assigns, to each of the multiple reception branches, the received signals for which synchronization timing is controlled with each of the multiple synchronization candidates,

the signal quality monitoring section monitors the signal quality of the received signal in each of the multiple reception branches, and

the synchronization candidate selecting section selects, as final reception timing, a synchronization candidate corresponding to a reception branch in which the received signal has the best quality based on predetermined selection criteria.

5. The synchronizing circuit according to claim 1, wherein

the synchronization candidate timing control section controls synchronization of the preamble of the reception packet with each of the multiple synchronization candidates, and

the signal quality monitoring section monitors the signal quality for the preamble synchronized with each of the multiple synchronization candidates.

6. The synchronizing circuit according to claim 1, wherein

the signal quality monitoring section estimates each channel matrix from the reception preamble synchronized with each of the multiple synchronization candidates and monitors a matrix norm of an inverse matrix of each channel matrix as the signal quality, and

the synchronization candidate selecting section selects, as the final reception timing, a synchronization candidate used for synchronization of the received signal with the smallest norm.

7. The synchronizing circuit according to claim 1 applied to an orthogonal frequency division multiplexing (OFDM) modulation receiver, wherein:

the signal quality monitoring section monitors, as the signal quality, an amount of phase rotation after a FFT operation of the reception preamble synchronized with each of the multiple synchronization candidates, and

the synchronization candidate selecting section selects, as the final reception timing, a synchronization candidate used for synchronization of the received signal with the smallest amount of phase rotation.

8. The synchronizing circuit according to claim 1, wherein:

the signal quality monitoring section monitors, as the signal quality, a likelihood obtained during decoding of the received signal synchronized with each of the multiple synchronization candidates, and

the synchronization candidate selecting section selects, as the final reception timing, a synchronization candidate used for synchronization of the received signal with the highest likelihood.

9. The synchronizing circuit according to claim 1, wherein:

the signal quality monitoring section monitors, as the signal quality, an error rate before decoding of a known received signal synchronized with each of the multiple synchronization candidates, and

the synchronization candidate selecting section selects, as the final reception timing, a synchronization candidate used for synchronization of the received signal with the lowest error rate.

10. The synchronizing circuit according to claim 1, wherein:

the signal quality monitoring section monitors, as the signal quality, an error rate after decoding of a known received signal synchronized with each of the multiple synchronization candidates, and

the synchronization candidate selecting section selects, as the final reception timing, a synchronization candidate used for synchronization of the received signal with the lowest error rate.

11. The synchronizing circuit according to claim 1, wherein:

the signal quality monitoring section monitors, as the signal quality, noise estimated from the reception preamble synchronized with each of the multiple synchronization candidates, and

the synchronization candidate selecting section selects, as the final reception timing, a synchronization candidate used for synchronization of the received signal with the lowest noise.

12. The synchronizing circuit according to claim 1 applied to an OFDM modulation receiver, wherein:

the preamble of the packet has a 1/N bandwidth of a fast Fourier transform (FFT) operation bandwidth (N is a positive number greater than

     2),

the synchronization candidate timing control section sets up M synchronization candidates for each reception branch (M is a positive integer of from 2 to N), controls synchronization timing with each of the multiple synchronization candidates, and shifts frequency of (M−

1) received signals so that all of the received signals are arranged within the FFT operation bandwidth and assigned to a single reception branch,

the signal quality monitoring section monitors the signal quality of the received signal after the FFT operation in the reception branch, and

the synchronization candidate selecting section selects, as the final reception timing, a synchronization candidate corresponding to a reception branch in which the received signal has the best quality on the basis of predetermined selection criteria.

13. The synchronizing circuit according to claim 1, wherein:

the preamble used to determine the final reception timing consists of N or more repetitions of known training signals (N is a positive number greater than

     2), and

the synchronization candidate timing control section sets up M synchronization candidates for each reception branch (M is a positive integer of from 2 to N), and assigns, to a single reception branch, M received signals in which a preamble of K-th repetition of which synchronization timing is controlled with K-th synchronization candidate (K is a positive integer from 1 to M).

14. A synchronizing method comprising the steps of:

coarse synchronizing to determine temporary reception timing using a preamble consisting of repetition of known training signals added to a reception packet;

controlling synchronization candidate timing to set up multiple synchronization candidates on the basis of the temporary reception timing and controlling synchronization of received signals in each of the multiple synchronization candidates, a first, a second, and a third synchronization candidate from the multiple synchronization candidates set at the temporary reception timing minus a predetermined time period, at the temporary reception timing, and at the temporary reception timing plus the predetermined time period, respectively, the first, second, and third synchronization candidates processed at the same time;

monitoring signal quality of the received signals synchronized in each of the multiple synchronization candidates; and

selecting one of the synchronization candidates as final reception timing on the basis of a monitoring result of the signal quality in the signal quality monitoring section.

15. A wireless communication device comprising:

a reception section which receives a packet with a preamble consisting of repetitions of known training sequences added at the head; and

a synchronizing circuit which includes;

a coarse synchronizing circuit which determines temporary reception timing using a reception preamble,

a synchronization candidate timing control section which sets up multiple synchronization candidates on the basis of the temporary reception timing and controls synchronization of received signals in each of the multiple synchronization candidates, a first, a second, and a third synchronization candidate from the multiple synchronization candidates set at the temporary reception timing minus a predetermined time period, at the temporary reception timing, and at the temporary reception timing plus the predetermined time period, respectively, the first, second, and third synchronization candidates processed at the same time,

a signal quality monitoring section which monitors signal quality of the received signals synchronized in each of the multiple synchronization candidates, and

a synchronization candidate selecting section which selects one of the synchronization candidates as a final reception timing on the basis of a monitoring result of the signal quality in the signal quality monitoring section,

wherein a reception process is conducted in which information signals received after the preamble are synchronized at the final reception timing.

16. A wireless communication method comprising the steps of:

receiving a packet with a preamble consisting of repetitions of known training sequences added at the head;

synchronizing, which includes;

determining temporary reception timing using a reception preamble,

setting up multiple synchronization candidates on the basis of the temporary reception timing and controlling synchronization of received signals in each of the multiple synchronization candidates, a first, a second, and a third synchronization candidate from the multiple synchronization candidates set at the temporary reception timing minus a predetermined time period, at the temporary reception timing, and at the temporary reception timing plus the predetermined time period, respectively, the first, second, and third synchronization candidates processed at the same time; and

monitoring signal quality of the received signals synchronized in each of the multiple synchronization candidates, and

selecting one of the synchronization candidates as a final reception timing on the basis of a monitoring result of the signal quality; and

conducting a reception process in which information signals received after the preamble is synchronized at the final reception timing.

17. A non-transitory computer readable storage medium having executable instructions stored therein, which when executed by a processor in a computer causes the processor to execute a method comprising:

determining temporary reception timing using a preamble consisting of repetitions of known training signals added to a reception packet;

setting up multiple synchronization candidates on the basis of the temporary reception timing and controls synchronization of received signals in each of the multiple synchronization candidates, a first, a second, and a third synchronization candidate from the multiple synchronization candidates set at the temporary reception timing minus a predetermined time period, at the temporary reception timing, and at the temporary reception timing plus the predetermined time period, respectively, the first, second, and third synchronization candidates processed at the same time;

monitoring signal quality of the received signals synchronized in each of the multiple synchronization candidates; and

selecting one of the synchronization candidates as final reception timing on the basis of a monitoring result of the signal quality in the signal quality monitoring section.

18. A synchronizing circuit comprising:

a coarse synchronizing circuit which determines temporary reception timing using a preamble consisting of repetitions of known training signals added to a received packet;

a synchronization candidate timing control section which sets up multiple synchronization candidates on the basis of the temporary reception timing and controls synchronization of received signals in each of the multiple synchronization candidates;

a signal quality monitoring section which monitors signal quality of the received signals synchronized in each of the multiple synchronization candidates; and

a synchronization candidate selecting section which selects one of the synchronization candidates as final reception timing on the basis of a monitoring result of the signal quality in the signal quality monitoring section, wherein

the signal quality monitoring section estimates each channel matrix from the reception preamble synchronized with each of the multiple synchronization candidates and monitors a matrix norm of an inverse matrix of each channel matrix as the signal quality, and

the synchronization candidate selecting section selects, as the final reception timing, a synchronization candidate used for synchronization of the received signal with the smallest norm.

19. A synchronizing circuit comprising:

a coarse synchronizing circuit which determines temporary reception timing using a preamble consisting of repetitions of known training signals added to a received packet;

a synchronization candidate timing control section which sets up multiple synchronization candidates on the basis of the temporary reception timing and controls synchronization of received signals in each of the multiple synchronization candidates;

a signal quality monitoring section which monitors signal quality of the received signals synchronized in each of the multiple synchronization candidates; and

a synchronization candidate selecting section which selects one of the synchronization candidates as final reception timing on the basis of a monitoring result of the signal quality in the signal quality monitoring section, wherein

the synchronizing circuit is applied to an orthogonal frequency division multiplexing (OFDM) modulation receiver,

the signal quality monitoring section monitors, as the signal quality, an amount of phase rotation after a FFT operation of the reception preamble synchronized with each of the multiple synchronization candidates, and

the synchronization candidate selecting section selects, as the final reception timing, a synchronization candidate used for synchronization of the received signal with the smallest amount of phase rotation.

20. A synchronizing circuit comprising:

a coarse synchronizing circuit which determines temporary reception timing using a preamble consisting of repetitions of known training signals added to a received packet;

a synchronization candidate timing control section which sets up multiple synchronization candidates on the basis of the temporary reception timing and controls synchronization of received signals in each of the multiple synchronization candidates;

a signal quality monitoring section which monitors signal quality of the received signals synchronized in each of the multiple synchronization candidates; and

a synchronization candidate selecting section which selects one of the synchronization candidates as final reception timing on the basis of a monitoring result of the signal quality in the signal quality monitoring section, wherein

the synchronizing circuit is applied to an OFDM modulation receiver,

the preamble of the packet has a 1/N bandwidth of a fast Fourier transform (FFT) operation bandwidth (N is a positive number greater than

     2),

the synchronization candidate timing control section sets up M synchronization candidates for each reception branch (M is a positive integer of from 2 to N), controls synchronization timing with each of the multiple synchronization candidates, and shifts frequency of (M−

1) received signals so that all of the received signals are arranged within the FFT operation bandwidth and assigned to a single reception branch,

the signal quality monitoring section monitors the signal quality of the received signal after the FFT operation in the reception branch, and

the synchronization candidate selecting section selects, as the final reception timing, a synchronization candidate corresponding to a reception branch in which the received signal has the best quality on the basis of predetermined selection criteria.