DSP block for implementing large multiplier on a programmable integrated circuit device

• US 8,307,023 B1
• Filed: 10/10/2008
• Issued: 11/06/2012
• Est. Priority Date: 10/10/2008
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Leung, Wai-Bor, Lui, Henry Y.
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US12/249,051
• Time in Patent Office: 1,488 Days
• Field of Search: None
• US Class Current: 708/625
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers

Abstract

A programmable integrated circuit device includes a plurality of specialized processing blocks. Each specialized processing block may be small enough to occupy a single row of logic blocks. The specialized processing blocks may be located adjacent one another in different logic block rows, forming a column of adjacent specialized processing blocks. Each specialized processing block includes one or more multipliers based on carry-save adders whose outputs are combined using compressors. Chain-in and chain-out connections to the compressors allow adjacent specialized processing blocks to be cascaded to form arbitrarily large multipliers. Each specialized processing block also includes a carry-propagate adder, and the carry-propagate added in the final specialized processing block of the chain provides the final result. The size of the multiplication that may be performed is limited only by the number of specialized processing blocks in the programmable integrated circuit device.

Claims

1. A specialized processing block for a programmable integrated circuit device having a plurality of instances of said specialized processing block, each instance of said specialized processing block comprising:

multiplier circuitry that performs at least one multiplication and provides partial sum/carry signals for each said at least one multiplication;

a chain output for propagating partial sum/carry signals to any other of said instances of said specialized processing block;

a chain input for receiving partial sum/carry signals propagated from any other of said instances of said specialized processing block;

combining circuitry that combines said partial sum/carry signals for each said at least one multiplication and any said partial sum/carry signals propagated from any other of said instances of said specialized processing block, for propagation to said chain output; and

circuitry for programmably routing signals within said specialized processing block.

2. The specialized processing block of claim 1, wherein each of said instances of said specialized processing block further comprises:

carry-propagate adder circuitry for adding output of said combining circuitry and generating a carry-out signal;

a carry output for propagating said carry-out signal to other of said instances of said specialized processing block; and

a carry input for receiving a carry-out signal from any other of said instances of said specialized processing block as a carry-in signal to said carry-propagate adder circuitry.

3. The specialized processing block of claim 2 wherein said circuitry for programmably routing signals within said specialized processing block comprises carry bypass circuitry for directly connecting said carry input to said carry output.

4. The specialized processing block of claim 3 wherein said circuitry for programmably routing signals within said specialized processing block further comprises chain bypass circuitry for directly connecting said chain input to said chain output.

5. The specialized processing block of claim 2 wherein said circuitry for programmably routing signals within said specialized processing block comprises chain bypass circuitry for directly connecting said chain input to said chain output.

6. The specialized processing block of claim 1 wherein said multiplication circuitry performs a plurality of multiplications.

7. The specialized processing block of claim 6 wherein said multiplication circuitry performs two multiplications.

8. The specialized processing block of claim 1 wherein said multiplication circuitry comprises at least one carry-save adder.

9. The specialized processing block of claim 1 wherein said combining circuitry comprises at least one compressor.

10. The specialized processing block of claim 1 wherein:

said multiplier circuitry performs a plurality of multiplications; and

said combining circuitry comprises;

a first compressor for combining outputs of said plurality of multiplications, and

a second compressor for combining output of said first compressor with said partial sum/carry signals propagated from any other of said instances of said specialized processing block on said chain input.

11. The specialized processing block of claim 1 wherein said circuitry for programmably routing signals within said specialized processing block comprises chain bypass circuitry for directly connecting said chain input to said chain output.

12. A programmable integrated circuit device comprising a plurality of specialized processing blocks, each of said specialized processing blocks comprising:

multiplier circuitry that performs at least one multiplication of a first size and provides partial sum/carry signals for each said at least one multiplication;

a chain output for propagating partial sum/carry signals to another said specialized processing block;

a chain input for receiving partial sum/carry signals propagated from another said specialized processing block;

combining circuitry that combines said partial sum/carry signals for each said at least one multiplication and any said partial sum/carry signals propagated from another said specialized processing block, for propagation to said chain output; and

circuitry for programmably routing signals within said specialized processing block;

wherein;

a number of said specialized processing blocks are chained together to perform a multiplication larger than said first size.

13. The programmable integrated circuit device of claim 12 wherein said plurality of specialized processing blocks are adjacent one another.

14. The programmable integrated circuit device of claim 12 wherein each said specialized processing block further comprises:

carry-propagate adder circuitry for adding output of said combining circuitry and generating a carry-out signal;

a carry output for propagating said carry-out signal to another said specialized processing block; and

a carry input for receiving a carry-out signal from a different said specialized processing block as a carry-in signal to said carry-propagate adder circuitry.

15. The programmable integrated circuit device of claim 14 wherein said circuitry for programmably routing signals within said specialized processing block comprises chain bypass circuitry for directly connecting said chain input to said chain output.

16. The programmable integrated circuit device of claim 15 wherein said circuitry for programmably routing signals within said specialized processing block comprises carry bypass circuitry for directly connecting said carry input to said carry output.

17. The programmable integrated circuit device of claim 14 wherein said circuitry for programmably routing signals within said specialized processing block comprises carry bypass circuitry for directly connecting said carry input to said carry output.

18. The programmable integrated circuit device of claim 12 wherein, in each said specialized processing block, said multiplication circuitry performs a plurality of multiplications.

19. The programmable integrated circuit device of claim 18 wherein, in each said specialized processing block, said multiplication circuitry performs two multiplications.

20. The programmable integrated circuit device of claim 12 wherein, in each said specialized processing block, said multiplication circuitry comprises at least one carry-save adder.

21. The programmable integrated circuit device of claim 12 wherein, in each said specialized processing block, said combining circuitry comprises at least one compressor.

22. The programmable integrated circuit device of claim 12 wherein, in each said specialized processing block:

said multiplication circuitry performs a plurality of multiplications; and

said combining circuitry comprises;

a first compressor for combining outputs of said plurality of multiplications, and

a second compressor for combining output of said first compressor with said partial sum/carry signals propagated from another said specialized processing block on said chain input.

23. The programmable integrated circuit device of claim 12 wherein said circuitry for programmably routing signals within said specialized processing block comprises chain bypass circuitry for directly connecting said chain input to said chain output.

24. A programmable integrated circuit device comprising:

a plurality of specialized processing blocks programmably chained together to perform a multiplication of a first size;

wherein;

each said specialized processing block is programmably operable to independently perform a multiplication of a second size; and

said first size is larger than said second size.

25. The programmable integrated circuit device of claim 24 wherein each said specialized processing block comprises:

multiplier circuitry that performs at least one multiplication and provides partial sum/carry signals for each said at least one multiplication; and

combining circuitry that combines said partial sum/carry signals for each said at least one multiplication and any partial sum/carry signals propagated from another said specialized processing block.

26. The programmable integrated circuit device of claim 25 wherein each said specialized processing block further comprises:

carry-propagate adder circuitry for adding output of said combining circuitry and generating a carry-out signal;

a carry output for propagating said carry-out signal to another said specialized processing block; and

a carry input for receiving a carry-out signal from a different said specialized processing block as a carry-in signal to said carry-propagate adder circuitry.

27. The programmable integrated circuit device of claim 25 wherein, in each said specialized processing block, said multiplier circuitry comprises at least one carry-save adder.

28. The programmable integrated circuit device of claim 25 wherein each said specialized processing block further comprises:

a chain output for propagating partial sum/carry signals to another said specialized processing block; and

a chain input for receiving partial sum/carry signals propagated from another said specialized processing block.

29. The programmable integrated circuit device of claim 28 wherein, in each said specialized processing block:

said multiplier circuitry performs a plurality of multiplications; and

said combining circuitry comprises;

a first compressor for combining outputs of said plurality of multiplications, and

a second compressor for combining output of said first compressor with said partial sum/carry signals propagated from another said specialized processing block on said chain input.