Interconnect and a method for designing an interconnect

• US 8,307,147 B2
• Filed: 09/09/2005
• Issued: 11/06/2012
• Est. Priority Date: 09/09/2005
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Goren, Ori, Netanel, Yaron
• Primary Examiner(s): Myers, Paul R
• Application Number:
  US12/066,229
• Publication Number:
  US 20080307145A1
• Time in Patent Office: 2,615 Days
• Field of Search: 710316-317, 710240-244
• US Class Current: 710/316
• CPC Class Codes: G06F 13/405 where the bridge performs a synchronising function
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for designing an interconnect, the method includes determining an amount of input ports, an amount of output ports; characterized by selecting multiple modular components such as to form an interconnect, whereas each modular component is selected from a group of modular components that are verified by parametric verification environment. An interconnect that includes multiple input ports and multiple output ports, characterized by including multiple modular components; whereas each modular component is adapted to support a certain point-to-point protocol; whereas at least one modular component includes a sampling circuit and a bypass circuit, whereas the sampling circuit is selectively bypassed by the bypass circuit.

Claims

1. An interconnect comprising:

multiple (M) input ports;

multiple (S) output ports; and

multiple modular components coupled between the M input ports and the S output ports;

wherein each modular component is adapted to support a certain point-to-point protocol, wherein at least one modular component comprises a sampling circuit and a first bypass circuit, the sampling circuit being selectively bypassed by the first bypass circuit, the multiple modular components comprising;

multiple expanders, wherein each expander comprises;

a sampler, wherein the sampler upgrades a transaction priority of a pending transaction request stored in the sampler by changing a priority attribute value of the transaction request, the sampler being selectively bypassed by a second bypass circuit; and

a de-multiplexer; and

multiple (S) arbiters and multiplexers, wherein different expanders are coupled to different masters, and wherein each expander is coupled in parallel to the S arbiters and multiplexers.

2. The interconnect according to claim 1 wherein the selective bypass of the first bypass circuit and of the second bypass circuit is responsive to an expected latency value of the interconnect.

3. The interconnect according to claim 1 wherein the modular components further comprise S splitters, wherein each splitter is adapted to transact information towards a slave associated with the splitter in response to at least one slave transaction characteristic.

4. The interconnect according to claim 1 adapted to perform a priority upgrade that comprises upgrading a priority of a certain pending transaction request and upgrading priority attributes of other transaction requests that precede the certain transaction request.

5. The interconnect according to claim 1 wherein the modular, components further comprise clock separators.

6. The interconnect according to claim 1 wherein the modular components further comprise bus width adaptors.

7. The interconnect according to claim 1 wherein the interconnect is adapted to implement time based priority upgrading that involves increasing a priority of a pending transport request that is pending for more than a certain time threshold.

8. The interconnect according to claim 1 wherein the interconnect is synthesized within a bounded centralized area generating a star topology.

9. The interconnect according to claim 1 wherein the modular components are adapted to alter arbitration priority indications of pending transaction requests.

19. The interconnect according to claim 1, wherein the multiple modular components comprise a first modular component supports a pending transaction request, wherein a transaction request that is associated with the pending transaction request is stored in a second modular component of the multiple modular components.

10. A method for designing an interconnect, the method comprises:

determining an amount of input ports, an amount of output ports;

selecting multiple modular components such as to form an interconnect, wherein each modular component is selected from a group of modular components that are verified by parametric verification environment, the multiple modular components comprising;

multiple arbiters and multiplexers; and

multiple expanders, wherein different expanders are coupled to different masters, and wherein each expander is coupled in parallel to S arbiters and multiplexers, and wherein each expander comprises a sampler and a de-multiplexer; and

selecting a main sampler that upgrades a transaction priority of pending transaction requests by changing priority attribute values of the pending transaction requests, the main sampler selectively bypassable by a first bypass circuit.

11. The method according to claim 10 further comprising determining whether to add a modular sampling component or to bypass at least one sampling circuit within at least one modular component;

wherein the determining is responsive to an expected interconnect latency value.

12. The method according to claim 10 wherein the selecting further comprises selecting at least one sampler in response to an expected interconnect latency value.

13. The method according to claim 10 comprising selecting a modular component arranged to implement time based priority upgrading that involves increasing a priority of a pending transport request that is pending for more than a certain time threshold.

14. The method according to claim 10 wherein the selecting comprises selecting S splitters, wherein each splitter is adapted to optimize transactions towards a slave associated with the splitter.

15. The method according to claim 10 wherein the selecting comprises selecting clock separators.

16. The method according to claim 10 wherein the selecting comprises selecting bus width adaptors.

20. The method according to claim 10, wherein the multiple modular components further comprise a respective modular component that receives and generates signals that represent a beginning and an end of a phase for a transaction, wherein the phase includes an request and address phase, a data phase, and an end of transaction phase adapted to perform a priority upgrade that comprises upgrading a priority of a certain pending transaction request and upgrading priority attributes of other transaction requests that precede the certain transaction request.

17. An interconnect comprising:

multiple (M) input ports;

multiple (S) output ports; and

multiple modular components coupled between the M input ports and the S output ports;

wherein each modular component is adapted to support a certain point-to-point protocol, the certain point to point protocol comprising a three phase protocol including a request and address phase, a data phase, and an end of transaction phase, wherein at least one modular component comprises a sampling circuit and a bypass circuit, the sampling circuit being selectively bypassed by the bypass circuit, the sampling circuit to upgrade a priority of a pending transaction request by changing a priority attribute value of the pending transaction request, the multiple modular components comprising;

multiple expanders; and

multiple (S) arbiters and multiplexers, wherein different expanders are coupled to different masters, and wherein each expander is coupled in parallel to the S arbiters and multiplexers;

wherein the interconnect is operable to locally terminate a transaction that is within the interconnect.

18. The interconnect according to claim 17 adapted to perform a priority upgrade that comprises upgrading a priority of a certain pending transaction request and upgrading priority attributes of other transaction requests that precede the certain transaction request.