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Relaxed memory consistency model

  • US 8,307,194 B1
  • Filed: 08/18/2003
  • Issued: 11/06/2012
  • Est. Priority Date: 08/18/2003
  • Status: Active Grant
First Claim
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1. A computer processing method comprising:

  • providing a computer system having a shared memory and a multistream processor (MSP), wherein the MSP includes a plurality of single stream processors (SSPs) including a first SSP, each one of the plurality of SSPs having a scalar section and one or more vector sections, wherein each of the plurality of SSPs is operatively coupled to the memory;

    defining program order between operations on the first SSP;

    defining operation dependence order of vector memory references to the memory with respect to each other and with respect to scalar memory references to the memory;

    maintaining a minimal guarantee on the ordering using an active list located in the scalar section, wherein maintaining includes;

    placing each instruction in order in the active list, wherein placing includes initializing each instruction to a speculative status;

    determining if the speculative status instruction is branch speculative or trap speculative;

    if the speculative status instruction is neither branch speculative nor trap speculative, checking to see if all scalar operands for the speculative status instruction are present;

    if all scalar operands for the speculative status instruction are present, moving the speculative status instruction to a “

    scalar committed”

    status and issuing a scalar commitment notice from the active list to the one or more vector sections;

    checking to see if all vector operands for the scalar committed status instruction are present;

    if all vector operands for the scalar committed status instruction are present, moving the scalar committed status instruction to a “

    committed”

    status;

    checking to see if all instructions previous to the committed status instruction are completed; and

    if all instructions previous to the committed status instruction are completed, moving the committed status instruction to a “

    graduated”

    status; and

    maintaining memory consistency between multiple vector memory references and between vector and scalar memory references by guaranteeing no vector store reference can be sent to memory prior to a scalar or vector load that occurs earlier in the program order.

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