Interconnection techniques

• US 8,307,265 B2
• Filed: 03/09/2009
• Issued: 11/06/2012
• Est. Priority Date: 03/09/2009
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ganga, Ilango, Mellitz, Richard
• Primary Examiner(s): LAMARRE, GUY J
• Application Number:
  US12/381,205
• Publication Number:
  US 20100229071A1
• Time in Patent Office: 1,338 Days
• Field of Search: 714/776, 714/752, 370/470, 370/510, 370/536
• US Class Current: 714/776
• CPC Class Codes: H03M 13/05 using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits H03M13/2906 takes precedence
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H04L 1/0052 Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/40 Transmitting circuits; Receiving circuits repeater circuits, relay circuits H04L25/20
• CPC Class Codes: H04L 5/1446 of transmission speed
• CPC Class Codes: H05K 7/1439 Back panel mother boards

Abstract

Techniques are described that can be used to extend the data transmission rate specified by 10GBASE-KR of IEEE 802.3ap (2007) to more than 10 Gb/s using a multiple lane backplane. A signal for transmission over 10 Gb/s can be divided into multiple streams for transmission over multiple lanes. Multiple transceiver pairs can be used for transmission and receipt of the multiple streams. Each transceiver pair may comply with 10GBASE-KR of IEEE 802.3ap (2007).

Claims

1. A system comprising:

a backplane comprising at least two lanes, wherein each lane comprises at least two pairs of differential traces on a printed circuit board and a connector coupled to transmit signals to each of the pairs, wherein each of the lanes is to transmit electrical signals, wherein electrical characteristics of each of the lanes is to comply in part with clause 72 of IEEE 802.3ap (2007);

at least two receivers;

at least two transmitters; and

logic to form a signal, wherein to form a signal, the logic is to combine contents of signals received by the receivers from the lanes, wherein

each of the at least two transmitters is associated with a receiver,

the backplane is to communicatively couple a transmitter to an associated receiver using a lane,

each transmitter is to transmit signals to an associated receiver,

each transmitter comprises;

forward error correction (FEC) encoder logic to encode signals with forward error correction, and

FEC decoder logic to decode received signals and to indicate error more often than every eighth sync bit, and

an aggregate transmission rate of the signals transmitted over the multiple lanes is approximately a number of lanes times a transmission rate of 10GBASE-KR in IEEE 802.3ap (2007).

2. The system of claim 1, further comprising a line card and wherein the line card comprises at least one of the at least two transmitters and at least one of the at least two receivers.

3. The system of claim 1, wherein each transmitter comprises logic to independently train an associated receiver using a PRBS11 training pattern, wherein each training pattern used on a lane is random with respect to patterns used on other lanes and further comprises logic to report a link as trained in response to all lanes being successfully trained.

4. The system of claim 1, wherein each of the transmitters further comprises:

logic to indicate an ability to transmit at 40 Gb/s over backplane using a technology bit A3 and

logic to auto-negotiate a transmission rate at any speed selected from a group consisting of 1 Gb/s, 10 Gb/s, and 40 Gb/s.

5. The system of claim 1, wherein each of the receivers further comprises:

logic to negotiate forward error correction on a single lane and

logic to apply the negotiated forward error correction to signals received on all lanes.

6. The system of claim 1, wherein each of the receivers further comprises:

logic to receive multiple signals over multiple lanes, wherein the multiple signals include FEC frame markers and

logic to use FEC frame markers on each of the lanes to align data on all of the lanes.

7. The system of claim 1, wherein each of the receivers further comprises:

a decoupling capacitor to decouple a receiver from a corresponding transmitter.

8. The system of claim 1, wherein the signals transmitted over each of the lanes include differential NRZ signals.

9. The system of claim 1, further comprising:

a first integrated circuit including a media access controller (MAC);

a second integrated circuit including a PHY; and

an XLAUI interface to communicatively couple the first integrated circuit to the second integrated circuit.

10. The system of claim 1, further comprising:

an integrated circuit including a MAC and a PHY and

an XLAUI interface to communicatively couple the MAC and PHY within the integrated circuit.

11. The system of claim 1, wherein for 40 Gbps transmission, each lane of four lanes is to carry transmit and receive bit streams tx_bit<

0;

3>

and rx_bit<

0;

3>

.

12. The system of claim 1, wherein a startup protocol per lane, signaling speed, and test methodology and procedures of the traces are to comply with clause 72 and annex 69A of IEEE standard 802.3ap (2007).

13. A method comprising:

receiving a source signal;

providing signals based on the source signal for transmission over multiple lanes of a backplane;

transmitting the signals over the multiple lanes, wherein transmitting over each of the multiple lanes complies with 10GBASE-KR of IEEE 802.3ap (2007), wherein

an aggregate transmission rate of the signals transmitted over the multiple lanes is approximately a number of lanes times a transmission rate of 10GBASE-KR of IEEE 802.3ap (2007);

independently training each transmitter associated with each of the lanes using a PRBS11 training pattern, wherein a training pattern used for each lane is random with respect to training patterns used on other lanes; and

indicating a global link signal detect after completion of training on all lanes.

14. The method of claim 13, further comprising:

indicating an ability to transmit at 40 Gb/s using a technology bit A3.

15. The method of claim 13, further comprising:

auto-negotiating a transmission rate at any speed selected from a group consisting of 1 Gb/s, 10 Gb/s, and 40 Gb/s.

16. The method of claim 13, further comprising:

negotiating forward error correction on a single lane and

applying the negotiated forward error correction to all lanes.

17. The method of claim 13, further comprising:

receiving the si1gnals over the multiple lanes, wherein the signals include FEC frame markers and

using FEC frame markers on each of the lanes to align data on all of the lanes.

18. A method comprising:

providing communicative coupling to lanes, wherein the providing communicative coupling to lanes comprises receiving signals transmitted over the lanes, wherein electrical characteristics of each of the lanes comply in part with clause 72 of IEEE 802.3ap (2007) and wherein an aggregate transmission rate of the signals received from the lanes is approximately a number of lanes times a transmission rate of 10GBASE-KR in IEEE 802.3ap (2007);

decoding the received signals from the lanes, the signals encoded using forward error correction (FEC); and

in response to detecting error based on the decoding, indicating error more often than every eighth sync bit.

19. The method of claim 18, further comprising:

negotiating forward error correction on a single lane and

applying the negotiated forward error correction to signals received on all lanes.

20. The method of claim 18, further comprising:

receiving signals over multiple lanes, wherein the received signals include FEC frame markers and

using FEC frame markers on each of the lanes to align data on all of the lanes.

21. The method of claim 18, wherein the signals transmitted over each of the lanes include differential NRZ signals.

22. The method of claim 18, wherein a startup protocol per lane, signaling speed, and test methodology and procedures comply with clause 72 and annex 69A of IEEE standard 802.3ap (2007).

23. An apparatus comprising:

a connector to provide communicative coupling with multiple lanes in response to coupling with the multiple lanes and to receive signals transmitted using the lanes, wherein the connector is to receive signals transmitted over the lanes, wherein electrical characteristics of each of the lanes is to comply in part with clause 72 of IEEE 802.3ap (2007) and wherein an aggregate transmission rate of the signals received from the lanes is approximately a number of lanes times a transmission rate of 10GBASE-KR in IEEE 802.3ap (2007) and

a forward error correction (FEC) decoder to decode received signals from the lanes and, in response to detection of error by the FEC decoder, to indicate error more often than every eighth sync bit.

24. The apparatus of claim 23, further comprising a line card that comprises the connector and FEC decoder logic.

25. The apparatus of claim 23, further comprising:

logic to negotiate forward error correction on a single lane and

logic to apply the negotiated forward error correction to signals received on all lanes.

26. The apparatus of claim 23, further comprising:

logic to receive multiple signals over multiple lanes, wherein the multiple signals include FEC frame markers and

logic to use FEC frame markers on each of the lanes to align data on all of the lanes.

27. The apparatus of claim 23, further comprising:

a decoupling capacitor to decouple a receiver from a corresponding transmitter.

28. An apparatus comprising:

a connector to provide communicative coupling with multiple lanes of a backplane in response to coupling with the multiple lanes;

at least one trainer configured to;

independently train a transmitter associated with one lane using a PRBS 11 training pattern, wherein a training pattern used for each lane is random with respect to training patterns used on other lanes and

indicate a global link signal detect after completion of training on all lanes; and

a transmitter to cause transmission of signals over the multiple lanes, wherein;

the signals are based on a source signal and

an aggregate transmission rate of the signals transmitted over the multiple lanes is approximately a number of lanes times a transmission rate of 10GBASE-KR of IEEE 802.3ap (2007).

29. The apparatus of claim 28, wherein the transmitter is to:

indicate an ability to transmit at 40 Gb/s over backplane using a technology bit A3 and

auto-negotiate a transmission rate at any speed among at least 1 Gb/s, 10 Gb/s, and 40 Gb/s.

30. The apparatus of claim 28, wherein the signals transmitted over each of the lanes include differential NRZ signals.

31. The apparatus of claim 28, further comprising:

a first integrated circuit including a media access controller (MAC);

a second integrated circuit including a PHY; and

an XLAUI interface to communicatively couple the first integrated circuit to the second integrated circuit.

32. The apparatus of claim 28, further comprising:

an integrated circuit including a MAC and a PHY and

an XLAUI interface to communicatively couple the MAC and PHY within the integrated circuit.