Electronic device wafer level scale packages and fabrication methods thereof
First Claim
1. A fabrication method for an electronic device chip scale package, comprising:
- providing a semiconductor wafer with a plurality of electronic devices thereon;
bonding the semiconductor wafer with a supporting substrate and thinning the back of the semiconductor wafer;
etching the back of the semiconductor wafer to create a first opening;
conformably depositing an insulating layer on the back of the semiconductor wafer;
etching the insulating layer at the bottom of the first opening and creating a second opening exposing part of contact pads, the exposed part of the contact pads comprising a vertical portion and a horizontal portion, wherein the second opening extends over upper surfaces of the contact pads, and lower surfaces of the contact pads are between the upper surfaces and the semiconductor wafer;
after the second opening is created, conformably depositing a conductive layer on the back of the semiconductor wafer and patterning the conductive layer, thereby creating an S-shaped connection constructed by the conductive layer and the contact pads;
forming exterior connections and terminal contact pads connecting the S-shaped connection; and
forming a dam structure between the semiconductor wafer and the supporting substrate, wherein the second opening extends into the dam structure, and a bottom surface of the second opening is between upper surfaces of the dam structure and the upper surfaces of the contact pads.
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Abstract
Electronic device wafer level scale packages and fabrication methods thereof. A semiconductor wafer with a plurality of electronic devices formed thereon is provided. The semiconductor wafer is bonded with a supporting substrate. The back of the semiconductor substrate is thinned. A first trench is formed by etching the semiconductor exposing an inter-layered dielectric layer. An insulating layer is conformably deposited on the back of the semiconductor substrate. The insulating layer on the bottom of the first trench is removed to create a second trench. The insulating layer and the ILD layer are sequentially removed exposing part of a pair of contact pads. A conductive layer is conformably formed on the back of the semiconductor. After the conductive layer is patterned, the conductive layer and the contact pads construct an S-shaped connection. Next, an exterior connection and terminal contact pads are subsequently formed.
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Citations
10 Claims
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1. A fabrication method for an electronic device chip scale package, comprising:
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providing a semiconductor wafer with a plurality of electronic devices thereon; bonding the semiconductor wafer with a supporting substrate and thinning the back of the semiconductor wafer; etching the back of the semiconductor wafer to create a first opening; conformably depositing an insulating layer on the back of the semiconductor wafer; etching the insulating layer at the bottom of the first opening and creating a second opening exposing part of contact pads, the exposed part of the contact pads comprising a vertical portion and a horizontal portion, wherein the second opening extends over upper surfaces of the contact pads, and lower surfaces of the contact pads are between the upper surfaces and the semiconductor wafer; after the second opening is created, conformably depositing a conductive layer on the back of the semiconductor wafer and patterning the conductive layer, thereby creating an S-shaped connection constructed by the conductive layer and the contact pads; forming exterior connections and terminal contact pads connecting the S-shaped connection; and forming a dam structure between the semiconductor wafer and the supporting substrate, wherein the second opening extends into the dam structure, and a bottom surface of the second opening is between upper surfaces of the dam structure and the upper surfaces of the contact pads. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification