Method for fabricating semiconductor device

• US 8,309,450 B2
• Filed: 09/16/2011
• Issued: 11/13/2012
• Est. Priority Date: 03/30/2011
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ohashi, Takuo
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US13/234,410
• Publication Number:
  US 20120252201A1
• Time in Patent Office: 424 Days
• Field of Search: 438/201, 438/211, 438/257, 438/258, 438/264, 438/266, 438592-594, 257/E21.679
• US Class Current: 438/592
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

According to one embodiment, a method for fabricating a semiconductor device including a memory cell portion and a select gate portion, the method includes etching a charge accumulation layer, a tunnel insulating film, and a semiconductor substrate to make a trench, burying a first insulating film in the trench to contact with a side surface of the charge accumulation layer, performing heat processing to compress the first insulating film, forming a second insulating film on the charge accumulation layer and the first insulating film, etching the second insulating film in the select gate portion to expose a surface of the charge accumulation layer, forming a silicon layer to contact with the exposed surface of the charge accumulation layer, forming a metal layer on the silicon layer, and performing heat processing to silicide an entire boundary region between the charge accumulation layer and the tunnel insulating film.

Claims

1. A method for fabricating a semiconductor device including a memory cell portion and a select gate portion, the method comprising:

forming a tunnel insulating film on a semiconductor substrate;

forming a charge accumulation layer on the tunnel insulating film;

etching the charge accumulation layer, the tunnel insulating film, and the semiconductor substrate to make a trench for isolating elements;

burying a first insulating film in the trench to contact with a side surface of the charge accumulation layer;

performing heat processing to compress the first insulating film;

forming a second insulating film on the charge accumulation layer and the first insulating film;

etching the second insulating film in the select gate portion to expose a surface of the charge accumulation layer;

forming a silicon layer to contact with the exposed surface of the charge accumulation layer;

forming a metal layer on the silicon layer; and

performing heat processing to silicide an entire boundary region between the charge accumulation layer and the tunnel insulating film.

2. The method according to claim 1, further comprising making a pinhole in the charge accumulation layer by chemical treatment of the charge accumulation layer after etching the second insulating film and before forming the silicon layer.

3. The method according to claim 1, further comprising, in the etching of the second insulating film, further etching the charge accumulation layer in the select gate portion.

4. The method according to claim 1, wherein the first insulating film is polysilazane.

5. The method according to claim 1, wherein the charge accumulation layer has an impurity concentration greater than or equal to a solid solubility limit of the charge accumulation layer.

6. The method according to claim 1, wherein the first insulating film is compressed to apply tensile stress to the charge accumulation layer.

7. The method according to claim 1, further comprising removing a mask material for forming the trench by wet etching, after compressing the first insulating film and before forming the second insulating film.

8. The method according to claim 1, wherein the charge accumulation layer in the select gate portion is fully silicided.

9. The method according to claim 1, wherein the semiconductor device is a NAND flash memory.

10. A method for fabricating a semiconductor device including a memory cell portion and a select gate portion, the method comprising:

forming a tunnel insulating film on a semiconductor substrate;

forming a charge accumulation layer on the tunnel insulating film;

etching the charge accumulation layer, the tunnel insulating film, and the semiconductor substrate to make a trench for isolating elements;

burying a first insulating film in the trench to contact with a side surface of the charge accumulation layer;

performing heat processing to compress the first insulating film;

forming a second insulating film on the charge accumulation layer and the first insulating film;

forming a first silicon layer on the second insulating film;

etching the first silicon layer and second insulating film in the select gate portion to expose a surface of the charge accumulation layer;

forming a second silicon layer on the first silicon layer and the charge accumulation layer to cover the first silicon layer and connect to the exposed surface of the charge accumulation layer;

forming a metal layer on the second silicon layer; and

performing heat processing to silicide the charge accumulation layer in the select gate portion which contacts the tunnel insulating film, thus silicidating an entire boundary region between the charge accumulation layer and the tunnel insulating film.

11. The method according to claim 10, further comprising making a pinhole in the charge accumulation layer by chemical treatment of the charge accumulation layer after etching the second insulating film and before forming the second silicon layer.

12. The method according to claim 10, further comprising, in the etching of the second insulating film, further etching the charge accumulation layer in the select gate portion.

13. The method according to claim 10, wherein the first insulating film is polysilazane.

14. The method according to claim 10, wherein the charge accumulation layer has an impurity concentration greater than or equal to a solid solubility limit of the charge accumulation layer.

15. The method according to claim 10, wherein the first insulating film is compressed to apply tensile stress to the charge accumulation layer.

16. The method according to claim 10, further comprising removing a mask material for forming the trench by wet etching, after compressing the first insulating film and before forming the second insulating film.

17. The method according to claim 10, wherein the charge accumulation layer in the select gate portion is fully silicided.

18. The method according to claim 10, wherein the semiconductor device is a NAND flash memory.