Semiconductor device, display device, and electronic appliance

• US 8,309,961 B2
• Filed: 10/04/2010
• Issued: 11/13/2012
• Est. Priority Date: 10/08/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Sakakura, Masayuki, Watanabe, Ryosuke, Sakata, Junichiro, Akimoto, Kengo, Miyanaga, Akiharu, Hirohashi, Takuya, Kishida, Hideyuki
• Primary Examiner(s): Nguyen, Khiem D
• Application Number:
  US12/897,419
• Publication Number:
  US 20110084266A1
• Time in Patent Office: 771 Days
• Field of Search: 257/43, 257/52, 257/57, 257/59, 257/E51.005, 257/49, 438/149, 438/150, 438/151, 438/158
• US Class Current: 257/59
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

In a channel protected thin film transistor in which a channel formation region is formed using an oxide semiconductor, an oxide semiconductor layer which is dehydrated or dehydrogenated by a heat treatment is used as an active layer, a crystal region including nanocrystals is included in a superficial portion in the channel formation region, and the rest portion is amorphous or is formed of a mixture of amorphousness/non-crystals and microcrystals, where an amorphous region is dotted with microcrystals. By using an oxide semiconductor layer having such a structure, a change to an n-type caused by entry of moisture or elimination of oxygen to or from the superficial portion and generation of a parasitic channel can be prevented and a contact resistance with a source and drain electrodes can be reduced.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a first oxide insulating layer in contact with part of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer in contact with part of the oxide semiconductor layer,

wherein a region of the oxide semiconductor layer located directly underneath a gap between the source electrode and the first oxide insulating layer, and a region of the oxide semiconductor layer located directly underneath a gap between the drain electrode and the first oxide insulating layer, each has a thickness less than a region overlapping with the source electrode layer, a region overlapping with the first oxide insulating layer, and a region overlapping with the drain electrode layer.

2. The semiconductor device according to claim 1, wherein the first oxide insulating layer is selected from the group consisting of a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film and an aluminum oxynitride film.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains indium, gallium and zinc.

4. An electronic appliance, wherein the semiconductor device according to claim 1 is used.

5. The semiconductor device according to claim 1,

wherein a second oxide insulating layer is formed over the first oxide insulating layer,

wherein the second oxide insulating layer is in contact with the oxide semiconductor layer located underneath the gap between the source electrode and the first oxide insulating layer, and

wherein the second oxide insulating layer is in contact with the oxide semiconductor layer located underneath the gap between the drain electrode and the first oxide insulating layer.

6. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a first oxide insulating layer in contact with part of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer in contact with part of the oxide semiconductor layer,

wherein a region of the oxide semiconductor layer located directly underneath a gap between the source electrode and the first oxide insulating layer, and a region of the oxide semiconductor layer located directly underneath a gap between the drain electrode and the first oxide insulating layer, each has a thickness less than a region overlapping with the source electrode layer, a region overlapping with the first oxide insulating layer, and a region overlapping with the drain electrode layer, and

wherein a portion of the oxide semiconductor layer which is in contact with the first oxide insulating layer has a crystal region.

7. The semiconductor device according to claim 6, wherein the first oxide insulating layer is selected from the group consisting of a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film and an aluminum oxynitride film.

8. The semiconductor device according to claim 6, wherein the oxide semiconductor layer contains indium, gallium and zinc.

9. The semiconductor device according to claim 6, wherein a nanocrystal which is c-axis oriented in a direction perpendicular to a surface of the oxide semiconductor layer is formed in the crystal region.

10. An electronic appliance, wherein the semiconductor device according to claim 6 is used.

11. The semiconductor device according to claim 6,

wherein a second oxide insulating layer is formed over the first oxide insulating layer,

wherein the second oxide insulating layer is in contact with the oxide semiconductor layer located underneath the gap between the source electrode and the first oxide insulating layer, and

wherein the second oxide insulating layer is in contact with the oxide semiconductor layer located underneath the gap between the drain electrode and the first oxide insulating layer.

12. A display device comprising:

a pixel portion and a driver circuit portion over a substrate, the pixel portion and the driver circuit portion each including a thin film transistor,

wherein the thin film transistor comprises;

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a first oxide insulating layer in contact with part of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer in contact with part of the oxide semiconductor layer,

wherein a region of the oxide semiconductor layer located directly underneath a gap between the source electrode and the first oxide insulating layer, and a region of the oxide semiconductor layer located directly underneath a gap between the drain electrode and the first oxide insulating layer, each has a thickness less than a region overlapping with the source electrode layer, a region overlapping with the first oxide insulating layer, and a region overlapping with the drain electrode layer.

13. The display device according to claim 12, wherein the first oxide insulating layer is selected from the group consisting of a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film and an aluminum oxynitride film.

14. The display device according to claim 12, wherein the oxide semiconductor layer contains indium, gallium and zinc.

15. An electronic appliance, wherein the display device according to claim 12 is used.

16. The semiconductor device according to claim 12,

wherein a second oxide insulating layer is formed over the first oxide insulating layer,

wherein the second oxide insulating layer is in contact with the oxide semiconductor layer located underneath the gap between the source electrode and the first oxide insulating layer, and

wherein the second oxide insulating layer is in contact with the oxide semiconductor layer located underneath the gap between the drain electrode and the first oxide insulating layer.

17. A display device comprising:

a pixel portion and a driver circuit portion over a substrate, the pixel portion and the driver circuit portion each including a thin film transistor,

wherein the thin film transistor comprises;

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor layer over the gate insulating layer;

a first oxide insulating layer in contact with part of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer in contact with part of the oxide semiconductor layer,

wherein a region of the oxide semiconductor layer located directly underneath a gap between the source electrode and the first oxide insulating layer, and a region of the oxide semiconductor layer located directly underneath a gap between the drain electrode and the first oxide insulating layer, each has a thickness less than a region overlapping with the source electrode layer, a region overlapping with the first oxide insulating layer, and a region overlapping with the drain electrode layer, and

wherein a portion of the oxide semiconductor layer which is in contact with the first oxide insulating layer has a crystal region.

18. The display device according to claim 17, wherein the first oxide insulating layer is selected from the group consisting of a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film and an aluminum oxynitride film.

19. The display device according to claim 17, wherein the oxide semiconductor layer contains indium, gallium and zinc.

20. The display device according to claim 17, wherein a nanocrystal which is c-axis oriented in a direction perpendicular to a surface of the oxide semiconductor layer is formed in the crystal region.

21. An electronic appliance, wherein the display device according to claim 17 is used.

22. The semiconductor device according to claim 17,

wherein a second oxide insulating layer is formed over the first oxide insulating layer,

wherein the second oxide insulating layer is in contact with the oxide semiconductor layer located underneath the gap between the source electrode and the first oxide insulating layer, and

wherein the second oxide insulating layer is in contact with the oxide semiconductor layer located underneath the gap between the drain electrode and the first oxide insulating layer.