Devices, structures, and methods using self-aligned resistive source extensions

• US 8,310,006 B2
• Filed: 09/21/2010
• Issued: 11/13/2012
• Est. Priority Date: 09/21/2009
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A., Darwish, Mohamed N., Zeng, Jun
• Primary Examiner(s): Arora, Ajay K
• Application Number:
  US12/887,303
• Publication Number:
  US 20110193131A1
• Time in Patent Office: 784 Days
• Field of Search: 257/139, 257/335
• US Class Current: 257/335
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 29/0839 Cathode regions of thyristors
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Devices, structures, and related methods for IGBTs and the like which include a self-aligned series resistance at the source-body junction to avoid latchup. The series resistance is achieved by using a charged dielectric, and/or by using a dielectric which provides a source of dopant atoms of the same conductivity type as the source region, at a sidewall adjacent to the source region.

Claims

1. A field-effect-gated bipolar active device, comprising:

a source region having a first conductivity type;

a body region having a second conductivity type, and surrounding said source region;

a gate which is capacitively coupled to said body region, to thereby create a channel portion therein which allows passage of majority carriers from said source region;

a source extension region which connects said source region to said channel, and is more resistive than said source region;

a drift/drain region which has said first conductivity type, and which is interposed between said body region and a second-conductivity-type collector region;

wherein said source extension region is generated by a dielectric layer which contains immobile net electrostatic charge;

wherein said source extension region has the same predominant dopant type as said body region, but is in inversion.

2. The device of claim 1, wherein said first conductivity type is n-type.

3. The device of claim 1, wherein said dielectric layer is inhomogeneous.

4. The device of claim 1, wherein said dielectric layer is primarily composed of silicon dioxide.

5. The device of claim 1, wherein said body region and said drift/drain region consist primarily of silicon.

6. The device of claim 1, wherein said gate and said channel are substantially planar.

7. The device of claim 1, wherein said gate is a trench gate, and said channel is substantially vertical.

8. The device of claim 1, wherein said gate is isolated from said body by a grown dielectric layer.

9. The device of claim 1, wherein said gate is a patterned thin film layer, and said dielectric layer is a filament which runs along at least some sidewalls of said gate.

10. A semiconductor device structure, comprising:

a source region having a first conductivity type;

a body region having a second conductivity type, and surrounding said source region;

a gate which is capacitively coupled to said body region, to thereby create a channel portion therein which allows passage of majority carriers from said source region;

a source extension region which connects said source region to said channel, and is more resistive than said source region;

a drift/drain region having said first conductivity type, and interposed between said body region and a second-conductivity-type collector region;

a first metallization layer connected to said source region and to a second-conductivity-type emitter region which is connected to said body region; and

a second metallization layer which is connected to said collector region;

wherein said source extension region is generated by a dielectric layer which contains immobile net electrostatic charge;

wherein said source extension region has the same predominant dopant type as said body region, but is in inversion.

11. The device of claim 10, wherein said first conductivity type is n-type.

12. The device of claim 10, wherein said gate is a trench gate, and said channel is substantially vertical.

13. The device of claim 10, wherein said gate is a patterned thin film layer, and said dielectric layer is a filament which runs along at least some sidewalls of said gate.

14. A field-effect-gated bipolar active device, comprising:

a source region having a first conductivity type;

a body region having a second conductivity type, and surrounding said source region;

a gate which is capacitively coupled to said body region, to thereby create a channel portion therein which allows passage of majority carriers from said source region;

a source extension region which connects said source region to said channel, and has said first conductivity type, and is more resistive than said source region;

a drift/drain region which has said first conductivity type, and which is interposed between said body region and a second-conductivity-type collector region;

wherein said source extension region lies under a dielectric layer which contains dopant atoms which predominantly correspond to said first conductivity type.

15. The device of claim 14, wherein said gate and said channel are substantially planar.