Reconfigurable sequencer structure

• US 8,310,274 B2
• Filed: 03/04/2011
• Issued: 11/13/2012
• Est. Priority Date: 09/06/2002
• Status: Expired due to Term

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Martin Vorbach
• Inventors: Vorbach, Martin
• Primary Examiner(s): LE, DON P
• Application Number:
  US13/040,769
• Publication Number:
  US 20110148460A1
• Time in Patent Office: 620 Days
• Field of Search: 326 37- 41, 326/46
• US Class Current: 326/38
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components

Abstract

A cell element field for data processing, having function cell means for execution of algebraic and/or logic functions and memory cell means for receiving, storing and/or outputting information is described. Function cell-memory cell combinations are formed in which a control connection leads from the function cell means to the memory cell means.

Claims

1. A field of cell elements for data processing, the field comprising:

a plurality of function cells, each (a) adapted for executing at least one of algebraic and logic functions and (b) including at least one arithmetic logic unit (ALU);

a plurality of memory cells adapted for at least one of receiving, storing, and outputting processing data; and

a configurable bus system adapted for being sequentially configured during program runtime into a plurality of different configurations that each provides a respective set of connections of memory cells of the plurality of memory cells to function cells of the plurality of function cells, different ones of the plurality of different configurations being used for processing of different respective sequential parts of the program via the respective connections of the configurations;

wherein;

the sets of connections differ between at least some of the different configurations; and

for each function cell to memory cell connection of the sets of connections, the function cell of the respective connection controls memory accesses of the memory cell of the respective connection.

2. The field as recited in claim 1, wherein at least one of a processor, coprocessor, and microcontroller configures at least one of respective functions and interconnection a plurality of the function cells and memory cells.

3. The field as recited in claim 1, wherein at least one of the arithmetic logic units is formed as an extended ALU.

4. The field as recited in claim 1, wherein the memory cells include at least one of volatile and nonvolatile data memories.

5. The field as recited in claim 1, wherein the memory cells of at least some of the connections store data to be processed.

6. The field as recited in claim 1, wherein a memory cell of at least one of the connections is adapted for sending stored information one of directly and indirectly to the respective connection leading to a respective function cell of the connection in response to triggering by the respective function cell.

7. The field as recited in claim 1, wherein a memory cell of at least one of the connections is adapted for sending stored information indirectly to the respective connection leading to a respective function cell of the connection, the indirect sending being via a backward register situated between the respective memory cell and function cell.

8. The field as recited in claim 1, wherein each of the memory cells is situated to receive information from at least one of the function cell which controls it, an input-output cell, and one of the function cells that does not control it.

9. The field as recited in claim 1, wherein, for each of at least one of the connections, at least one input-output cell is assigned to the connection for at least one of sending information to and receiving information from at least one of an external unit, a function cell that is not part of the connection, another one of the connections, and a memory cell that is not part of the connection.

10. The field as recited in claim 9, wherein the input-output cell assigned to the connection is adapted for receiving control commands from the function cell of the connection to which it is assigned.

11. The field as recited in claim 9, wherein, for the each of the at least one of the connections, at least one of (a) the function cell of the respective connection is adapted for transmitting, and (b) at least one of the memory cell and the input-output cell of the respective connection is adapted for decoding, at least some of the following commands:

DATA WRITE/READ, ADDRESS POINTER WRITE/READ, PROGRAM POINTER WRITE/READ, PROGRAM POINTER INCREMENT, STACK POINTER WRITE/READ, PUSH, POP, OPCODE, and FETCH.

12. The field as recited in claim 1, wherein, for each of at least one of the connections, the function cell of the connection is a sole master for controlling access of the connection.

13. The field as recited in claim 1, wherein at least one of the function cells is situated adjacent to at least one of:

(a) at least one of the memory cells and (b) an input-output cell.

14. The field as recited in claim 1, further comprising at least one input-output cell, wherein the plurality of functions cells, the plurality of memory cells, and the at least one input-output cell are arranged in a multidimensional matrix of rows and columns, each of at least one of:

(a) at least one of the plurality of function cells, (b) at least one of the plurality of memory cells, and (c) at least one of the at least one input-output cell being adapted for receiving data from an upper row and outputting data into a lower row.

15. The field as recited in claim 1, wherein the memory cells of at least some of the connections store programs steps to be executed.

16. The field as recited in claim 1, wherein, for each of at least one of the connections, at least one of (a) the function cell of the respective connection is adapted for transmitting, and (b) the memory cell of the respective connection is adapted for decoding, at least some of the following commands:

DATA WRITE/READ, ADDRESS POINTER WRITE/READ, PROGRAM POINTER WRITE/READ, PROGRAM POINTER INCREMENT, STACK POINTER WRITE/READ, PUSH, POP, OPCODE, and FETCH.

17. The field as recited in claim 1, wherein the memory access control is performed by transmission of at least one of read-enable and write enable signals.

18. The field as recited in claim 14, wherein a single row of the matrix includes at least one of the plurality of function cells, at least one of the plurality of memory cells, and at least one of the at least one input-output cell.

19. A method for operating a field of cell elements for data processing, the field including:

(a) plurality of function cells each adapted for executing at least one of algebraic and logic functions and including at least one arithmetic logic unit (ALU), (b) a plurality of memory cells adapted for at least one of receiving, outputting, and storing processing data, and (c) a configurable bus system, the method comprising;

during runtime of a program, sequentially configuring the bus system into a plurality of different configurations that each provides a respective set of hardware connections of memory cells of the plurality of memory cells to function cells of the plurality of function cells; and

processing different respective sequential parts of the program by different respective ones of the plurality of different configurations via the respective connections of the configurations;

wherein;

the sets of connections differ between the different configurations; and

for each function cell to memory cell connection of the sets of connections, the function cell of the connection controls memory accesses of the memory cell of the connection.

20. The method as recited in claim 19, wherein each of at least one of the plurality of function cells is adapted for outputting for its memory access control at least some of the following control commands:

OPCODE FETCH, DATA WRITE INTERNAL, DATA WRITE EXTERNAL, DATA READ INTERNAL, DATA READ EXTERNAL, ADDRESS POINTER WRITE INTERNAL, ADDRESS POINTER WRITE EXTERNAL, ADDRESS POINTER READ INTERNAL, ADDRESS POINTER READ EXTERNAL, PROGRAM POINTER WRITE INTERNAL, PROGRAM POINTER WRITE EXTERNAL, PROGRAM POINTER READ INTERNAL, PROGRAM POINTER READ EXTERNAL, STACK POINTER WRITE INTERNAL, STACK POINTER WRITE EXTERNAL, STACK POINTER READ INTERNAL, STACK POINTER READ EXTERNAL, PUSH, POP, and PROGRAM POINTER INCREMENT.