Oscillator circuit

• US 8,310,316 B2
• Filed: 09/09/2008
• Issued: 11/13/2012
• Est. Priority Date: 09/28/2007
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Tanabe, Akira, Inoue, Naoya
• Primary Examiner(s): Chang, Joseph
• Assistant Examiner(s): SHIN, JEFFREY M
• Application Number:
  US12/680,504
• Publication Number:
  US 20100244972A1
• Time in Patent Office: 1,526 Days
• Field of Search: 331/107.R, 331/116.FE, 331/117.R, 331/167
• US Class Current: 331/117.R
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0086 on semiconductor substrate inductors for integrated circuits H01L28/10
• CPC Class Codes: H01L 23/64 Impedance arrangements
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/19104 on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1243 the means comprising voltage variable capacitance diodes
• CPC Class Codes: H03B 5/1287 the parameter being a quality factor, e.g. Q factor of the frequency determining element
• CPC Class Codes: H03B 5/1293 having means for achieving a desired tuning characteristic, e.g. linearising the frequency characteristic across the tuning voltage range
• CPC Class Codes: H03J 3/20 of single resonant circuit by varying inductance only or capacitance only

Abstract

A first wiring layer and a plurality of second wiring layers having a thickness smaller than the first wiring layer are stacked on the semiconductor substrate. An oscillator circuit has an inductor formed by the plurality of second wiring layers. The inductor oscillates at a frequency at which the inductor and a parasitic capacitance of an inverter circuit resonate. A drain of an n-type MISFET and a drain of a p-type MISFET of the inverter circuit are connected to each other, and an output of the inductor is connected to a connection point of those drains.

Claims

1. An on-chip oscillator circuit mounted on a semiconductor substrate, wherein a first wiring layer and a plurality of second wiring layers having a thickness smaller than the first wiring layer are stacked on the semiconductor substrate;

wherein the oscillator circuit comprises;

an inductor formed by the plurality of second wiring layers, and

an inverter circuit including an n-type MISFET and a p-type MISFET;

wherein the inductor is connected to the inverter circuit so as to operate as a load on the inverter circuit;

wherein the inductor is operable to oscillate at a frequency at which the inductor and a parasitic capacitance of the inverter circuit resonate;

wherein a drain of the n-type MISFET and a drain of the p-type MISFET are connected to each other, and an output of the inductor is connected to a connection point of those drains;

wherein the plurality of second wiring layers forming the inductor includes a first layer to an nth layer stacked on each other where n is an integer not less than 2,

each of the first layer to the nth layer extends substantially concentrically with respect to a common center from an outermost turn as a first turn to an innermost turn as an mth turn where m is an integer not less than 2 and has a discontinuous end in each turn,

wiring layers of the plurality of second wiring layers that are located vertically adjacent to each other are connected to each other through a via at a location at which each of the wiring layers has the discontinuous end such that currents flow in the same direction through the wiring layers,

turns located radially adjacent to each other in a wiring layer of the uppermost layer or the lowermost layer of the plurality of second wiring layers are connected to each other at a location at which each of the turns has the discontinuous end such that currents flow in the same direction through the turns,

the inductor is connected continuously from an end of the first turn of the first layer that is not connected to another turn to an end of the mth turn of the first layer or the nth layer that is not connected to another turn, and

currents flow in the same direction through turns stacked vertically adjacent to each other, and currents flow in the same direction through turns arranged adjacent to each other in each of the plurality of second wiring layers.

2. The oscillator circuit according to claim 1, further comprising a capacitor formed by using a semiconductor device or the first wiring layer or the second wiring layers,

wherein the inductor and the capacitor are connected in series or in parallel to each other,

the inductor oscillates at a frequency at which the inductor, the parasitic capacitance of the inverter circuit, and the capacitor resonate, and

an output of the capacitor is connected to the connection point at which the drains of the n-type MISFET and the p-type MISFET are connected to each other.

3. The oscillator circuit according to claim 1, further comprising an additional inductor magnetically coupled to the inductor,

wherein opposite ends of a switching element or a resistance element having a variable resistance are connected between an input end and an output end of the additional inductor, and the oscillation frequency of the oscillator circuit is varied by varying a resistance value of the switching element or the resistance element.

4. The oscillator circuit according to claim 3, wherein a value of at least 10¹¹ is obtained when an inductance value of the inductor is divided by a capacitance of the capacitor and multiplied by the oscillation frequency.

5. The oscillator circuit according to claim 1, further comprising a capacitor formed by using a semiconductor device or the first wiring layer or the second wiring layers and an additional inductor magnetically coupled to the inductor,

wherein the capacitor has a fixed capacitance,

the inductor and the capacitor are connected in series or in parallel to each other,

the inductor oscillates at a frequency at which the inductor, the parasitic capacitance of the inverter circuit, and the capacitor resonate,

an output of the capacitor is connected to the connection point at which the drains of the n-type MISFET and the p-type MISFET are connected to each other, and

opposite ends of a switching element or a resistance element having a variable resistance are connected between an input end and an output end of the additional inductor, and the oscillation frequency of the oscillator circuit is varied by varying a resistance value of the switching element or the resistance element.

6. The oscillator circuit according to claim 1, wherein the plurality of second wiring layers forming the inductor includes a first layer to an nth layer stacked on each other where n is an integer not less than 2,

each of the first layer to the nth layer extends substantially concentrically with respect to a common center from an outermost turn as a first turn to an innermost turn as an mth turn where m is an integer not less than 2 and has a discontinuous end in each turn,

the first layer to the nth layer have a substantially congruous shape as viewed in a plan view and are arranged without substantial deviation in a direction of rotation with respect to the common center,

an end of a (k−

1)th turn of a (j−

1)th layer is connected to an end of a (k−

1)th turn of a jth layer through a via where j is an integer ranging from 2 to n and k is an integer ranging from 2 to m,

another end of the (k−

1)th turn of the jth layer is connected to an end of the (k−

1)th turn of a (j+1)th layer in a case where j is smaller than n,

an end of a kth turn of the first layer that is opposite to an end connected to the second layer is connected to an end of the (k−

1)th turn of the first layer in a case where k is equal to m and is connected to an end of a (k+1)th turn of the first layer in a case where k is smaller than m,

an end of the kth turn of the nth layer that is not connected to the (n−

1)th layer is connected to an end of the (k−

1)th turn of the nth layer in a case where k is equal to m and is connected to an end of the (k+1)th turn of the nth layer in a case where k is smaller than m,

the inductor is connected continuously from an end of the first turn of the first layer that is not connected to another turn to an end of the mth turn of the first layer or the nth layer that is not connected to another turn,

currents flow in the same direction through turns stacked vertically adjacent to each other, and

currents flow in the same direction through turns arranged adjacent to each other in the same layer.

7. The oscillator circuit according to claim 1, wherein the plurality of second wiring layers forming the inductor have a capacitance per length between wires stacked vertically adjacent to each other that is larger than a capacitance per length between wires arranged adjacent to each other in the same layer.

8. The oscillator circuit according to claim 7, wherein the plurality of second wiring layers forming the inductor have an interval between wires arranged adjacent to each other in the same layer that is larger than an interval between wires stacked vertically adjacent to each other.

9. The oscillator circuit according to claim 7, wherein the inductor has a wire width that is larger than a thickness of the second wiring layers, which is a wire thickness of the inductor.

10. The oscillator circuit according to claim 2, wherein a value of at least 10¹¹ is obtained when an inductance value of the inductor is divided by a capacitance of the capacitor and multiplied by the oscillation frequency.

11. The oscillator circuit according to claim 1, wherein the inductor has a wire width that is equal to or less than 2 μ

m.

12. The oscillator circuit according to claim 1, wherein the MISFET included in the inverter circuit has a gate width that is equal to or less than 20 μ

m.

13. The oscillator circuit according to claim 1, wherein the oscillator circuit is configured to oscillate at a frequency that is n times as high as a required frequency where n is an integer and to perform 1/n frequency division on the oscillated output to thereby output the required frequency.