Camera arrangements with back lighting detection and methods of using same

• US 8,310,557 B1
• Filed: 07/02/2007
• Issued: 11/13/2012
• Est. Priority Date: 10/12/2001
• Status: Active Grant

• Current Assignee: C47 Technologies LLC
• Original Assignee: Worldscape, Inc. (Capital One Financial Corporation)
• Inventors: Rogina, Peter R.
• Primary Examiner(s): Nguyen, Quang N.
• Application Number:
  US11/824,972
• Time in Patent Office: 1,961 Days
• Field of Search: 348/425.3, 348/E5.058, 348/E5.083, 385/43
• US Class Current: 348/218.1
• CPC Class Codes: G06F 3/002 Specific input/output arrangements not covered by G06F3/01 - G06F3/16 other optical apparatus G02B27/00
• CPC Class Codes: G06F 3/011 Arrangements for interaction with the human body, e.g. for user immersion in virtual reality blind teaching G09B21/00
• CPC Class Codes: G06T 11/60 Editing figures and text; Combining figures or text
• CPC Class Codes: G06T 19/006 Mixed reality object pose determination, tracking or camera calibration for mixed reality G06T7/00
• CPC Class Codes: H04N 23/50 Constructional details
• CPC Class Codes: H04N 23/60 Control of cameras or camera modules
• CPC Class Codes: H04N 23/80 Camera processing pipelines; Components thereof
• CPC Class Codes: H04N 23/90 Arrangement of cameras or camera modules, e.g. multiple cameras in TV studios or sports stadiums
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

The present invention relates to camera arrangements with backlighting detection. The camera arrangements are capable of simultaneously capturing real scene data from various viewpoints. This data may include illumination data impinging the scene. The illumination data may then be utilized to alter the apparent illumination of a second image, either real or virtual, which is to be superimposed over the real scene so that the illumination across the entire superimposed scene is consistent. The camera arrangements may utilize combinations of umbilical cables and light tubes to expand or contract the field of capture. The camera arrangements may also include in-line signal processing of the data output.

Claims

1. A master camera array comprising:

a circuit board having front and rear surfaces, the circuit board defining a plurality of camera sites on said front surface, a control data input connection, a data output connection and a data bus extending along the circuit board to said camera sites;

a plurality of camera units, each such camera unit incorporating an imaging chip defining a plurality of pixels and a connection engaged with one of said camera sites so that each camera unit is connected to said data bus at one of said camera sites;

data output circuitry connected between said camera sites and said data output connection for merging pixel data provided by said plurality of camera units into a common data output stream; and

at least one illumination data capture unit mounted to said circuit board, said at least one illumination data capture unit incorporating a photosensitive chip such that said photosensitive chip may provide illumination data impinging on said photosensitive chip to said circuit board.

2. The master camera array as claimed in claim 1 wherein said data output circuitry connected between said camera sites and said data output connection comprises an image processing chip to provide processing of said output data.

3. The master camera array as claimed in claim 1 wherein the connections of at least some of said camera units are engaged with at least some of said camera sites through an umbilical cable so that such camera units can be physically moved with respect to the circuit board.

4. The master camera array as claimed in claim 1 wherein some of said camera units include light tubes connected to the imaging chip such that said pixel data may be obtained remote from said imaging chip through said light tubes.

5. The master camera array as claimed in claim 1 wherein said camera units are physically mounted on the front surface of said circuit board.

6. The master camera as claimed in claim 5, further comprising a frame and a plurality of circuit boards mounted to said frame.

7. The master camera array as claimed in claim 6 wherein the camera units mounted on each of said circuit boards are spaced apart from one another by a uniform distance, and wherein camera units on adjacent boards are spaced apart from one another by the same distance.

8. The master camera array as claimed in claim 6, wherein said common data output stream from each circuit board may be combined into a master common data output stream, said master common data output stream capable of being parsed to identify each of said common data output streams from each of said circuit boards.

9. The master camera array as claimed in claim 6 wherein said data output circuitry connected between said camera sites and said output connection of each circuit board comprises an image processing chip to provide processing of said output data.

10. The master camera array as claimed in claim 9 wherein each of said circuit boards further includes a data sharing module and wherein said master camera array further includes a data sharing bus, each of said data sharing modules being in communication with said data sharing bus of each respective circuit board and said data sharing modules being in communication with each other via said data sharing bus.

11. The master camera array as claimed in claim 10 wherein said output data from any one circuit board of the master camera array may be processed by said image processing chip of another circuit board by communicating said output data of said any one circuit board to said another circuit board via said data sharing bus.

12. The master camera array as claimed in claim 1 wherein said circuit board is flexible.

13. The master camera array as claimed in claim 1 further comprising at least one illumination data capture unit mounted to said circuit board, said illumination data capture units incorporating a camera connected to said data output circuitry such that said camera may provide illumination data impinging on said camera to said data output circuitry.

14. The master camera array as claimed in claim 13, wherein said common data output stream may be parsed to identify each of said data outputs provided by said plurality of camera units.

15. The master camera array as claimed in claim 1, wherein said common data output stream may be parsed to identify each of said data outputs provided by said plurality of camera units and at least one illumination data capture unit.

18. A camera array as claimed in claim 1, wherein said illumination capture unit is mounted to the rear of said board.

16. A camera array comprising:

a circuit board having front and rear surfaces, the circuit board defining a plurality of accessory sites on said front surface, a control data input connection, a data output connection and a data bus extending along the circuit board to said accessory sites;

a plurality of camera units, each such camera unit incorporating an imaging chip defining a plurality of pixels and a connection engaged with one of said accessory sites so that each camera unit is connected at one of said accessory sites;

a plurality of sensors, each such sensor engaged with one of said accessory sites;

data output circuitry connected between said accessory sites and said data output connection for merging data provided by said plurality of camera units and said plurality of sensors into a common data output stream; and

at least one illumination data capture unit engaged with one of said accessory sites, said at least one illumination data capture unit incorporating a photosensitive chip such that said photosensitive chip may provide illumination data impinging on said photosensitive chip.

17. A camera array comprising:

a circuit board having front and rear surfaces, the circuit board defining a plurality of camera sites on said front surface, a control data input connection, a data output connection and a data bus extending along the circuit board to said camera sites;

a plurality of camera units, each such camera unit incorporating an imaging chip defining a plurality of pixels and a connection engaged with one of said camera sites so that each camera unit is connected to said data bus at one of said camera sites;

data output circuitry connected between said camera sites and said data output connection for merging pixel data provided by said plurality of cameras into a common data output stream;

wherein some of said cameras include light tubes having tip ends and root ends, the root ends connected to the imaging chip such that said pixel data may be obtained remote from said imaging chip through said light tube, said tip ends of said light tubes being spaced closer together than said root ends.

19. A camera array comprising:

a circuit board, the circuit board defining a plurality of camera sites, a control data input connection, a data output connection and a data bus extending along the circuit board to said camera sites;

a plurality of camera units, each such camera unit incorporating an imaging chip defining a plurality of pixels and a connection engaged with one of said camera sites so that each camera unit is connected to said data bus at one of said camera sites;

data output circuitry connected between said camera sites and said data output connection for merging pixel data provided by said plurality of cameras into a common data output stream;

at least one illumination data capture unit mounted to said circuit board, said at least one illumination data capture unit incorporating a photosensitive chip such that said photosensitive chip may provide illumination data impinging on said photosensitive chip.

20. The camera array of claim 19, wherein said common data output stream may be parsed to identify each of said data outputs provided by said plurality of camera units and at least one illumination data capture unit.

22. The camera array of claim 20, wherein said common data output stream may be parsed to identify each of said data outputs provided by said plurality of camera units.

21. A camera array comprising:

a circuit board having front and rear surfaces, the circuit board defining a plurality of camera sites on said front surface, a control data input connection, a data output connection and a data bus extending along the circuit board to said camera sites;

a plurality of camera units, each such camera unit incorporating an imaging chip defining a plurality of pixels and a connection engaged with one of said camera sites so that each camera unit is connected to said data bus at one of said camera sites;

data output circuitry connected between said camera sites and said data output connection for merging pixel data provided by said plurality of cameras into a common data output stream;

at least one illumination data capture unit mounted to said board, said at least one illumination data capture unit incorporating a camera such that said camera may provide illumination data impinging on said camera to said circuit board.

23. A master camera array comprising:

a frame and a plurality of circuit boards mounted to said frame, each circuit board having front and rear surfaces, said circuit boards defining a plurality of camera sites on said front surfaces, a control data input connection, a data output connection and a data bus extending along the circuit board to said camera sites;

a plurality of camera units, each such camera unit incorporating an imaging chip defining a plurality of pixels and a connection engaged with one of said camera sites so that each camera unit is connected to said data bus at one of said camera sites;

data output circuitry connected between said camera sites and said data output connection for merging pixel data provided by said plurality of cameras into a common data output stream;

wherein said common data output stream from each circuit board may be combined into a master common data output stream, said master common data output stream capable of being parsed to identify each of said common data output streams from each of said circuit boards.

24. A master camera array comprising:

a frame and a plurality of circuit boards mounted to said frame, each circuit board comprising;

a front surface defining a plurality of camera sites, a control data input connection, a data output connection, and a data bus extending along the circuit board to said camera sites;

a plurality of camera units, each such camera unit incorporating an imaging chip defining a plurality of pixels and a connection engaged with one of said camera sites so that each camera unit is connected to said data bus at one of said camera sites;

data output circuitry connected between said camera sites and said data output connection for merging pixel data provided by said plurality of cameras into a common data output stream, said data output circuitry comprising an image processing chip to provide processing of said output data; and

a data sharing module;

wherein said master camera array further comprises a data sharing bus, each of said data sharing modules being in communication with said data sharing bus of each respective circuit board and said data sharing modules being in communication with each other via said data sharing bus.

25. The master camera array as claimed in claim 24 wherein said output data from any one circuit board of the master array may be processed by said image processing chip of another circuit board by communicating said output data of said any one circuit board to said another circuit board via said data sharing bus.

26. A camera array comprising:

a circuit board, the circuit board defining a plurality of camera sites, a control data input connection, a data output connection and a data bus extending along the circuit board to said camera sites;

a plurality of camera units, each such camera unit incorporating an imaging chip defining a plurality of pixels and a connection engaged with one of said camera sites so that each camera unit is connected to said data bus at one of said camera sites;

data output circuitry connected between said camera sites and said data output connection for merging pixel data provided by said plurality of camera units into a common data output stream;

at least one illumination data capture unit mounted to said circuit board, said at least one illumination data capture unit incorporating a photosensitive chip such that said photosensitive chip may provide illumination data impinging on said photosensitive chip to said circuit board;

wherein said common data output stream may be parsed to identify each of said data outputs provided by said plurality of camera units and at least one illumination data capture unit.

27. A camera array comprising:

a circuit board, the circuit board defining a plurality of camera sites, a control data input connection, a data output connection and a data bus extending along the circuit board to said camera sites;

a plurality of camera units, each such camera unit incorporating an imaging chip defining a plurality of pixels and a connection engaged with one of said camera sites so that each camera unit is connected to said data bus at one of said camera sites;

data output circuitry connected between said camera sites and said data output connection for merging pixel data provided by said plurality of camera units into a common data output stream;

at least one illumination data capture unit mounted to said board, said at least one illumination data capture unit incorporating a camera connected to said data output circuitry such that said camera may provide illumination data impinging on said camera to said data output circuitry;

wherein said common data output stream may be parsed to identify each of said data outputs provided by said plurality of camera units.