Semiconductor memory device comprising a plurality of static memory cells

• US 8,310,883 B2
• Filed: 07/28/2011
• Issued: 11/13/2012
• Est. Priority Date: 08/10/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Yabuuchi, Makoto, Nii, Koji
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US13/193,258
• Publication Number:
  US 20110286291A1
• Time in Patent Office: 474 Days
• Field of Search: 365/189.11, 365/230.03, 365/230.06, 365/226
• US Class Current: 365/189.11
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

Claims

1. A semiconductor device comprising:

a plurality of static memory cells arranged in rows and columns;

a plurality of word lines provided corresponding to the rows, respectively, each word line coupled to the first and second access transistors of the memory cells in the corresponding row;

a plurality of word line drivers coupled to the plurality of word lines, respectively, each word line driver driving the word line coupled thereto to a selected state;

a driver power supply line coupled commonly to the plurality of word line drivers and applying a driver power supply voltage to the plurality of word line drivers as respective operation voltages thereof;

a driver power supply circuit receiving a power supply voltage, which is higher than the driver power supply voltage, on a main power supply node and providing the driver power supply line with the drive power supply voltage,

the driver power supply circuit including;

a first element coupled between the main power supply node and a couple node, and applying a current flowing from the main power supply node to the couple node, and

a second element coupled between the couple node and a ground node, and applying a current from the couple node to a ground node to step down a voltage on the couple node from the power supply voltage, the driver power supply circuit producing the driver power supply voltage based on the couple node.

2. The semiconductor device according to claim 1, wherein

the first element includes a resistance element.

3. The semiconductor device according to claim 2, wherein

the resistance element is a passive resistance element different from a transistor element.

4. The semiconductor device according to claim 1, wherein

the second element is so configured to allow an current quantity adjustment of the current flowing from the couple node to the ground node.

5. The semiconductor device according to claim 4, wherein

the second element includes a transistor coupled between the couple node and the ground node.

6. The semiconductor device according to claim 1, wherein

the second element includes a plurality of transistors coupled in parallel between the couple node and the ground node and having gate electrodes receiving distinct signals respectively.