Semiconductor memory device comprising a plurality of static memory cells
First Claim
1. A semiconductor device comprising:
- a plurality of static memory cells arranged in rows and columns;
a plurality of word lines provided corresponding to the rows, respectively, each word line coupled to the first and second access transistors of the memory cells in the corresponding row;
a plurality of word line drivers coupled to the plurality of word lines, respectively, each word line driver driving the word line coupled thereto to a selected state;
a driver power supply line coupled commonly to the plurality of word line drivers and applying a driver power supply voltage to the plurality of word line drivers as respective operation voltages thereof;
a driver power supply circuit receiving a power supply voltage, which is higher than the driver power supply voltage, on a main power supply node and providing the driver power supply line with the drive power supply voltage,the driver power supply circuit including;
a first element coupled between the main power supply node and a couple node, and applying a current flowing from the main power supply node to the couple node, anda second element coupled between the couple node and a ground node, and applying a current from the couple node to a ground node to step down a voltage on the couple node from the power supply voltage, the driver power supply circuit producing the driver power supply voltage based on the couple node.
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Accused Products
Abstract
A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.
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Citations
6 Claims
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1. A semiconductor device comprising:
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a plurality of static memory cells arranged in rows and columns; a plurality of word lines provided corresponding to the rows, respectively, each word line coupled to the first and second access transistors of the memory cells in the corresponding row; a plurality of word line drivers coupled to the plurality of word lines, respectively, each word line driver driving the word line coupled thereto to a selected state; a driver power supply line coupled commonly to the plurality of word line drivers and applying a driver power supply voltage to the plurality of word line drivers as respective operation voltages thereof; a driver power supply circuit receiving a power supply voltage, which is higher than the driver power supply voltage, on a main power supply node and providing the driver power supply line with the drive power supply voltage, the driver power supply circuit including; a first element coupled between the main power supply node and a couple node, and applying a current flowing from the main power supply node to the couple node, and a second element coupled between the couple node and a ground node, and applying a current from the couple node to a ground node to step down a voltage on the couple node from the power supply voltage, the driver power supply circuit producing the driver power supply voltage based on the couple node. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification