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Semiconductor memory device comprising a plurality of static memory cells

  • US 8,310,883 B2
  • Filed: 07/28/2011
  • Issued: 11/13/2012
  • Est. Priority Date: 08/10/2006
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a plurality of static memory cells arranged in rows and columns;

    a plurality of word lines provided corresponding to the rows, respectively, each word line coupled to the first and second access transistors of the memory cells in the corresponding row;

    a plurality of word line drivers coupled to the plurality of word lines, respectively, each word line driver driving the word line coupled thereto to a selected state;

    a driver power supply line coupled commonly to the plurality of word line drivers and applying a driver power supply voltage to the plurality of word line drivers as respective operation voltages thereof;

    a driver power supply circuit receiving a power supply voltage, which is higher than the driver power supply voltage, on a main power supply node and providing the driver power supply line with the drive power supply voltage,the driver power supply circuit including;

    a first element coupled between the main power supply node and a couple node, and applying a current flowing from the main power supply node to the couple node, anda second element coupled between the couple node and a ground node, and applying a current from the couple node to a ground node to step down a voltage on the couple node from the power supply voltage, the driver power supply circuit producing the driver power supply voltage based on the couple node.

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