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Semiconductor memory device

  • US 8,310,884 B2
  • Filed: 03/15/2010
  • Issued: 11/13/2012
  • Est. Priority Date: 08/06/2009
  • Status: Active Grant
First Claim
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1. A semiconductor memory device configured to selectively adopt a twin-cell configuration and a single-cell configuration, comprising:

  • a memory cell array comprising a plurality of memory cells arranged at intersections of word-lines and bit-lines;

    a sense amplifier circuit configured to sense and amplify a signal read from the memory cells;

    a write circuit configured to write, according to first data held in a first memory cell of the memory cells, second data corresponding to the first data to a second memory cell different from the first memory cell as second data corresponding to the first data, when the twin-cell configuration is selected, the second memory cell being connected to a sense amplifier circuit different from that connected to the first memory cell;

    a data latch circuit configured to hold data read from the first memory cell;

    a logic operation circuit configured to perform a logic operation using data read from the second memory cell and data held in the data latch circuit as input values, and output third data as an operation value; and

    a write-back circuit configured to write the third data back to the first memory cell.

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