Semiconductor memory device

• US 8,310,884 B2
• Filed: 03/15/2010
• Issued: 11/13/2012
• Est. Priority Date: 08/06/2009
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iwai, Takayuki, Fujii, Shuso, Miyano, Shinji
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US12/723,922
• Publication Number:
  US 20110032778A1
• Time in Patent Office: 974 Days
• Field of Search: 365/189.16, 365/189.14, 365/189.15, 365/189.011, 365/207, 365/196, 365/189.08
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/2236 Copy

Abstract

A sense amplifier circuit senses and amplifies a signal read from memory cells arranged at intersections of word-lines and bit-lines. A write circuit reads first data held in a first memory cell of the memory cells, and writes second data corresponding to the first data in a second memory cell different from the first memory cell. A data latch circuit holds data read from the first memory cell. A logic operation circuit performs a logic operation using data read from the second memory cell and data held in the data latch circuit as input values and outputs third data as an operation value. A write-back circuit writes the third data back to the first memory cell.

Claims

1. A semiconductor memory device configured to selectively adopt a twin-cell configuration and a single-cell configuration, comprising:

a memory cell array comprising a plurality of memory cells arranged at intersections of word-lines and bit-lines;

a sense amplifier circuit configured to sense and amplify a signal read from the memory cells;

a write circuit configured to write, according to first data held in a first memory cell of the memory cells, second data corresponding to the first data to a second memory cell different from the first memory cell as second data corresponding to the first data, when the twin-cell configuration is selected, the second memory cell being connected to a sense amplifier circuit different from that connected to the first memory cell;

a data latch circuit configured to hold data read from the first memory cell;

a logic operation circuit configured to perform a logic operation using data read from the second memory cell and data held in the data latch circuit as input values, and output third data as an operation value; and

a write-back circuit configured to write the third data back to the first memory cell.

2. The semiconductor memory device according to claim 1, wherein

the data latch circuit is a write data-latch circuit temporarily holding write data when writing data to the memory cell.

3. The semiconductor memory device according to claim 1, wherein

the logic operation circuit is adapted to perform different logic operations between when a memory cell in the memory cell array that is to be subjected to scrambled writing is read and when a memory cell not to be subjected to scrambled writing is read.

4. The semiconductor memory device according to claim 3, wherein

a pair of adjacent bit-lines form a complementary bit-line pair, and each complementary bit-line pair has one sense amplifier circuit connected thereto.

5. The semiconductor memory device according to claim 1, wherein

the write circuit is adapted to transfer a voltage of the first bit-line connected to the first memory cell to the second bit-line connected to the second memory cell.

6. The semiconductor memory device according to claim 1, further comprising a gate circuit configured to supply data held in the data latch circuit to the logic operation circuit in response to an enable signal.

7. The semiconductor memory device according to claim 1, wherein

the logic operation circuit comprising:

a first operation circuit configured to perform a first logic operation using data read from the second memory cell and data held in the data latch Circuits input values, and outputting fourth data;

a second operation circuit configured to perform a second logic operation using data read from the second memory cell and data held in the data latch circuit as input values, and outputting fifth data; and

a multiplexer configured to output the fourth data as the third data when a memory cell in the memory cell array that is to be subjected to scrambled writing is read, and output the fifth data as the third data when a memory cell not to be subjected to scrambled writing is read.

8. The semiconductor memory device according to claim 1, wherein the write circuit further comprises a transfer gate circuit configured to selectively form a current path between the first bit-line connected to the first memory cell and the second bit-line connected to the second memory cell.

9. The semiconductor memory device according to claim 8, wherein the transfer gate circuit is adapted to be rendered conductive when a signal read from the first memory cell is amplified by the sense amplifier circuit and appears on the first bit-line.

10. The semiconductor memory device according to claim 8, wherein

the logic operation circuit is adapted to perform different logic operations between when a memory cell in the memory cell array that is to be subjected to scrambled writing is read and when a memory cell not to be subjected to scrambled writing is read.

11. The semiconductor memory device according to claim 8, further comprising a gate circuit configured to supply data held in the data latch circuit to the logic operation circuit in response to an enable signal.

12. The semiconductor memory device according to claim 1, wherein

a pair of adjacent bit-lines form a complementary bit-line pair, and each complementary bit-line pair has one sense amplifier circuit connected thereto.

13. A semiconductor memory device comprising:

a memory cell array comprising a plurality of memory cells arranged at intersections of word-lines and bit-lines, each memory cell storing data by holding a charge in a capacitor;

a sense amplifier circuit configured to sense and amplify a signal read from the memory cell;

a read amplifier configured to further amplify an amplification signal from the sense amplifier circuit, and outputting read data;

a write circuit configured to write, in a normal operation, write data to the memory cell, the write data being to be written to the memory cell, and write, in a twin-cell configuration in which two memory cells hold the same data, a first data read from a first memory cell of the memory cells to a second memory cell different from the first memory cell as a second data corresponding to the first data, the second memory cell being connected to a sense amplifier circuit different from that connected to the first memory cell; and

a logic operation circuit configured to perform a logic operation using data read from the second memory cell and data read from the first memory cell as input values, and output third data as an operation value;

the write circuit writing the third data back to the first memory cell.

14. The semiconductor memory device according to claim 13, wherein

the logic operation circuit is adapted to perform different logic operations between when a memory cell in the memory cell array that is to be subjected to scrambled writing is read and when a memory cell not to be subjected to scrambled writing is read.

15. The semiconductor memory device according to claim 13, wherein

a pair of adjacent bit-lines form a complementary bit-line pair, and each complementary bit-line pair has one sense amplifier circuit connected thereto.

16. The semiconductor memory device according to claim 13, wherein

the complementary bit-line pair has a twisted bit-line structure in which the bit-line pair intersects with each other in predetermined regions.

17. The semiconductor memory device according to claim 13, wherein

the logic operation circuit comprises:

a first operation circuit configured to perform a first logic operation using data read from the second memory cell and data held in the data latch circuit as input values, and output fourth data;

a second operation circuit configured to perform a second logic operation using data read from the second memory cell and data held in the data latch circuit as input values, and output fifth data;

a multiplexer configured to output the fourth data as the third data when a memory cell in the memory cell array that is to be subjected to scrambled writing is read, and output the fifth data as the third data when a memory cell not to be subjected to scrambled writing is read.

18. The semiconductor memory device according to claim 13, wherein the write circuit further comprises a transfer gate circuit configured to selectively form a current path between the first bit-line connected to the first memory cell and the second bit-line connected to the second memory cell.