Programmable pre-emphasis circuit for serial ATA

• US 8,311,064 B1
• Filed: 06/02/2010
• Issued: 11/13/2012
• Est. Priority Date: 10/22/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Wu, Lei, Hu, Timothy
• Primary Examiner(s): Qureshi, Afsar M.
• Application Number:
  US12/792,247
• Time in Patent Office: 895 Days
• Field of Search: 370532-539, 341100-101, 710 5-305, 711114-168
• US Class Current: 370/534
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03025 using a two-tap delay line

Abstract

A transmitter including an analog front end configured to receive a serial signal; a control circuit configured to generate a first gain signal and a second gain signal based on a characteristic of a serial channel; a first amplifier is configured to amplify the serial signal to generate a first amplified signal based on the first gain signal; a first delay device configured to delay the serial signal to generate a first delayed signal; a second amplifier configured to amplify the first delayed signal to generate a second amplified signal based on the second gain signal; and at least one summer is configured to sum the first amplified signal and the second amplified signal to generate an output signal. The output signal is transmitted on the serial channel.

Claims

1. A transmitter comprising:

an analog front end configured to receive a serial signal;

a control circuit configured to generate a first gain signal and a second gain signal based on a characteristic of a serial channel;

a first amplifier configured to, based on the first gain signal, amplify the serial signal to generate a first amplified signal;

a first delay device configured to delay the serial signal to generate a first delayed signal;

a second amplifier configured to, based on the second gain signal, amplify the first delayed signal to generate a second amplified signal; and

at least one summer configured to sum the first amplified signal and the second amplified signal to generate an output signal, wherein the output signal is transmitted on the serial channel.

2. The transmitter of claim 1, wherein the control circuit is configured to provide pre-emphasis to one of the serial signal and the first delayed signal based on the characteristic of the serial channel by generating the second gain signal to be different than the first gain signal.

3. The transmitter of claim 2, wherein:

the characteristic of the serial channel is a band-limiting transmission characteristic; and

the control circuit is configured to provide the pre-emphasis to compensate for the band-limiting transmission characteristic.

4. The transmitter of claim 2, wherein the control circuit is preprogrammed based on at least one of (i) data stored in memory or (ii) data input to a physical layer of the transmitter.

5. The transmitter of claim 1, wherein the control circuit is configured to adjust a first magnitude of a first frequency of the output signal differently than a second magnitude of a second frequency of the output signal by generating the second gain signal to be different than the first gain signal.

6. The transmitter of claim 1, wherein the control circuit is configured to generate a third gain signal based on the characteristic of the serial channel, and wherein the transmitter further comprises:

a second delay device configured to delay the first delay signal to generate a second delayed signal; and

a third amplifier configured to amplify the second delayed signal to generate a third amplified signal based on the third gain signal,

wherein the at least one summer is configured to sum the first amplified signal, the second amplified signal and the third amplified signal to generate the output signal.

7. The transmitter of claim 6, wherein at least one of the first delay device or the second delay device provides a unit delay.

8. The transmitter of claim 6, wherein at least one of the first delay device or the second delay device provides a partial unit delay.

9. The transmitter of claim 6, wherein based on the characteristic of the serial channel, the control circuit is configured to (i) provide pre-emphasis to at least one of the serial signal, the first delayed signal or the second delayed signal and (ii) not provide pre-emphasis to at least one of the serial signal, the first delayed signal or the second delayed signal.

10. The transmitter of claim 6, wherein the control circuit is configured to generate a fourth gain signal based on the characteristic of the serial channel, and wherein the transmitter further comprises:

a third delay device configured to delay the second delay signal to generate a third delayed signal; and

a fourth amplifier configured to amplify the third delayed signal to generate a fourth amplified signal based on the fourth gain signal,

wherein the at least one summer is configured to sum the first amplified signal, the second amplified signal, the third amplified signal, and the fourth amplified signal to generate the output signal.

11. The transmitter of claim 1, wherein the analog front end comprises the first amplifier, the first delay device, the second amplifier and the at least one summer.

12. The transmitter of claim 11, wherein the analog front end is a serial advanced technology attachment device.

13. The transmitter of claim 1, wherein:

the first amplifier includes a first differential input and a first differential output, wherein the first differential input receives the serial signal, and wherein the first differential output outputs the first amplified signal; and

the second amplifier includes a second differential input and a second differential output, wherein the second differential input receives the first delayed signal, and wherein the second differential output outputs the second amplified signal.

14. A host device comprising:

the transmitter of claim 1; and

a multiplexer configured to (i) receive L signals including the serial signal and (ii) output the serial signal based on a control signal, wherein L is an integer greater than or equal to 2.

15. The host device of claim 14, wherein the multiplexer is configured to (i) receive the L signals and at a first frequency and (ii) output the serial signal at a second frequency.

16. The host device of claim 15, wherein the second frequency is equal to a product of L and the first frequency.

17. The host device of claim 15, wherein the second frequency is greater than 1.4 GHz.

18. A method of operating a transmitter, the method comprising:

receiving a serial signal;

generating a first gain signal and a second gain signal based on a characteristic of a serial channel;

based on the first gain signal, amplifying the serial signal to generate a first amplified signal;

delaying the serial signal to generate a first delayed signal;

based on the second gain signal, amplifying the first delayed signal to generate a second amplified signal;

summing the first amplified signal and the second amplified signal to generate an output signal; and

transmitting the output signal on the serial channel.

19. The method of claim 18, further comprising providing pre-emphasis to one of the serial signal and the first delayed signal based on the characteristic of the serial channel by generating the second gain signal to be different than the first gain signal.

20. The method of claim 18, further comprising:

generating a third gain signal based on the characteristic of the serial channel;

delaying the first delay signal to generate a second delayed signal;

amplifying the second delayed signal to generate a third amplified signal based on the third gain signal; and

summing the first amplified signal, the second amplified signal and the third amplified signal to generate the output signal.