Wireless transceiver and wireless transmission method
First Claim
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1. A wireless transceiver, comprising:
- a receiving part that includes an amplifying circuit that amplifies a received signal and an analog-to-digital converting circuit that converts the signal amplified by the amplifying circuit from analog to digital;
a transmitting part that includes a plurality of circuit blocks having different functions for transmitting a signal by wireless;
a switch that performs switching among output signals of the circuit blocks forming the transmitting part for selective input thereof to the amplifying circuit;
a DC offset compensating part capable of compensating for a DC offset occurring in the amplifying circuit; and
a controlling circuit that performs control to cancel or reduce a DC offset occurring in each of the plurality of circuit blocks based on a digital signal output from the analog-to-digital converting circuit when the output signal of each of the plurality of circuit blocks forming the transmitting part is selectively input to the amplifying circuit,wherein the controlling circuit includes a parameter setting part that sets a parameter for each of the plurality of circuit blocks forming the transmitting part so that the DC offset occurring in the circuit block is minimized, andthe parameter setting part includes;
a setting section that sets an input of a first circuit block of the plurality of circuit blocks forming the transmitting part to zero as an initial value;
a calculating section that measures an output value from each circuit block of the analog-to-digital converting circuit and calculates a DC offset value of each of the plurality of blocks of the transmitting part by removing the DC offset occurring in the amplifying circuit from the measured value; and
a checking section that changes an appropriate parameter so that the calculated DC offset value decreases to reset the parameter and repeats the calculation of the DC offset value and the reset of the appropriate parameter to check whether the DC offset value is minimized.
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Abstract
A DC offset of a VGA is measured by selecting a ground contact of a switch. Then, the gain of the VGA is set at an appropriate value, monitoring contacts of the switch are successively selected, and the output values of an ADC for the respective cases are measured with the input to a DAC set at zero. Then, the DC offset of the VGA is removed, the DC offset value of each circuit block, such as DAC, in a transmitting part is calculated, and parameters are set so that the DC offset value of each circuit block is minimized.
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Citations
1 Claim
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1. A wireless transceiver, comprising:
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a receiving part that includes an amplifying circuit that amplifies a received signal and an analog-to-digital converting circuit that converts the signal amplified by the amplifying circuit from analog to digital; a transmitting part that includes a plurality of circuit blocks having different functions for transmitting a signal by wireless; a switch that performs switching among output signals of the circuit blocks forming the transmitting part for selective input thereof to the amplifying circuit; a DC offset compensating part capable of compensating for a DC offset occurring in the amplifying circuit; and a controlling circuit that performs control to cancel or reduce a DC offset occurring in each of the plurality of circuit blocks based on a digital signal output from the analog-to-digital converting circuit when the output signal of each of the plurality of circuit blocks forming the transmitting part is selectively input to the amplifying circuit, wherein the controlling circuit includes a parameter setting part that sets a parameter for each of the plurality of circuit blocks forming the transmitting part so that the DC offset occurring in the circuit block is minimized, and the parameter setting part includes;
a setting section that sets an input of a first circuit block of the plurality of circuit blocks forming the transmitting part to zero as an initial value;
a calculating section that measures an output value from each circuit block of the analog-to-digital converting circuit and calculates a DC offset value of each of the plurality of blocks of the transmitting part by removing the DC offset occurring in the amplifying circuit from the measured value; and
a checking section that changes an appropriate parameter so that the calculated DC offset value decreases to reset the parameter and repeats the calculation of the DC offset value and the reset of the appropriate parameter to check whether the DC offset value is minimized.
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Specification
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Current AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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Original AssigneeKabushiki Kaisha Toshiba (Toshiba Corporation)
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InventorsAgawa, Kenichi
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Primary Examiner(s)LE, NHAN T
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Application NumberUS13/409,552Publication NumberTime in Patent Office257 DaysField of Search455/127.1, 455/127.2, 455/230, 455/232.1, 455/234.1, 455/240.1, 455/323, 455/324, 455/334, 375/345US Class Current455/240.1CPC Class CodesH04B 1/38 Transceivers, i.e. devices ...
