Processor chip including a plurality of cache elements connected to a plurality of processor cores

• US 8,312,200 B2
• Filed: 07/21/2010
• Issued: 11/13/2012
• Est. Priority Date: 06/10/1999
• Status: Expired due to Term

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Martin Vorbach, Nückel, Armin
• Inventors: Vorbach, Martin, Nückel, Armin
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US12/840,477
• Publication Number:
  US 20100287324A1
• Time in Patent Office: 846 Days
• Field of Search: 710305-313
• US Class Current: 710/313
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 8/433 Dependency analysis; Data or control flow analysis
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions

Abstract

Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.

Claims

1. A processor chip comprising:

an arrangement of a plurality of processor cores;

at least one memory controller for external main memory; and

a plurality of cache elements for caching data, the plurality of cache elements being located between and connected to the processor cores and the at least one memory controller;

wherein each of at least some of the plurality of processor cores;

operates as at least one of an accumulator processor, a stack processor, and a load/store processor; and

includes a unit for loading instructions defining at least one of a function and an interconnection of the respective processor core.

2. The processor chip according to claim 1, wherein the at least one memory controller is adapted to control external Random Access Memory (RAM).

3. The processor chip according to claim 1, wherein at least some of the processor cores are reconfigurable in at least one of function and interconnection.

4. The processor chip according to claim 1, wherein the at least one memory controller supports cache functions.

5. The processor chip according to claim 1, wherein the at least one memory controller has an associated memory management unit (MMU).

6. The processor chip according to claim 1, further comprising:

at least one of interface controller for peripheral devices.

7. The processor chip according to claim 1, wherein the each of the at least some of the plurality of processor cores is reconfigurable in at least one of its function and its interconnection as defined by the instructions and on a hardware level by changing its active circuitry paths.

8. The processor chip according to claim 7, wherein the at least one memory controller is adapted to control external Synchronous Dynamic Random Access Memory (SDRAM).

9. The processor chip according to claim 7, wherein the at least one memory controller is adapted to control external Rambus Dynamic Random Access Memory (RDRAM).

10. The processor chip according to claim 7, wherein the at least one memory controller has an associated cache TAG memory.

11. The processor chip according to claim 7, further comprising:

an Ethernet controller adapted for operating as an interface controller for peripheral devices.

12. The processor chip according to claim 7, further comprising:

a peripheral component interconnect (PCI) controller.

13. The processor chip according to claim 7, wherein the changing of the active circuitry paths is performed using a switching device.

14. The processor chip according to claim 7, wherein the at least one memory controller is adapted to control external Dynamic Random Access Memory (DRAM).

15. A processor chip comprising:

an arrangement of a plurality of processor cores;

at least one memory controller for Dynamic Random Access Memory (DRAM); and

a plurality of cache elements for caching data, the plurality of cache elements being located between and connected to the processor cores and the at least one memory controller;

wherein each of at least some of the processor cores;

operates as at least one of an accumulator processor, a stack processor, and a load/store processor; and

includes a unit for loading instructions defining at least one of a function and an interconnection of the respective processor core.

16. The processor chip according to claim 15, wherein the at least one memory controller is adapted to control external memory.

17. The processor chip according to claim 15, wherein the at least one memory controller is adapted to control external Random Access Memory (RAM).

18. The processor chip according to claim 15, wherein at least some of the processor cores are reconfigurable in at least one of function and interconnection.

19. The processor chip according to claim 15, wherein the at least one memory controller supports cache functions.

20. The processor chip according to claim 15, wherein the at least one memory controller has an associated memory management unit (MMU).

21. The processor chip according to claim 15, further comprising:

at least one interface controller for peripheral devices.

22. The processor chip according to claim 15, wherein the each of the at least some of the processor cores is reconfigurable in at least one of its function and its interconnection as defined by the instructions and on a hardware level by changing its active circuitry paths.

23. The processor chip according to claim 22, wherein the at least one memory controller is adapted to control external Rambus Dynamic Random Access Memory (RDRAM).

24. The processor chip according to claim 22, wherein the at least one memory controller has an associated cache TAG memory.

25. The processor chip according to claim 22, further comprising:

an Ethernet controller adapted for operating as an interface controller for peripheral devices.

26. The processor chip according to claim 22, further comprising:

a peripheral component interconnect (PCI) controller.

27. The processor chip according to claim 22, further comprising:

at least one interface controller for peripheral devices., wherein the at least one memory controller is adapted to control external Rambus Dynamic Random Access Memory (RDRAM).

28. The processor chip according to claim 22, further comprising:

at least one interface controller for peripheral devices, wherein the at least one memory controller has an associated cache TAG memory.

29. The processor chip according to claim 22, wherein the changing of the active circuitry paths is performed using a switching device.

30. The processor chip according to claim 22, wherein the at least one memory controller is adapted to control external Synchronous Dynamic Random Access Memory (SDRAM).

31. The processor chip according to claim 22, further comprising:

at least one interface controller for peripheral devices, wherein the at least one memory controller is adapted to control external Synchronous Dynamic Random Access Memory (SDRAM).

32. The processor chip according to claim 21, wherein the at least one memory controller is adapted to control external memory.

33. The processor chip according to claim 21, wherein the at least one memory controller is adapted to control external Random Access Memory RAM.

34. The processor chip according to claim 21, wherein the at least one memory controller supports cache functions.

35. The processor chip according to claim 21, wherein the at least one memory controller has an associated memory management unit (MMU).

39. The processor chip according to claim 31, wherein the at least interface controller is an Ethernet controller.

40. The processor chip according to claim 31, wherein the at least one interface controller is a peripheral component interconnect (PCI) controller.

41. The processor chip according to claim 31, wherein the at least one interface controller is a universal serial bus (USB) controller.

36. A processor chip comprising:

an arrangement of a plurality of processor cores;

at least one interface controller for peripheral devices; and

a plurality of cache elements for caching data, the plurality of cache elements being located between and connected to the processor cores and the at least one memory controller;

wherein each of at least some of the processor cores;

is reconfigurable in at least one of its function and its interconnection, and on a hardware level by changing, via a switching device, its active circuitry paths;

operates as at least one of an accumulator processor, a stack processor, and a load/store processor; and

includes a unit for loading instructions defining at least one of the function and the interconnection according to which the respective processor core is configured.

37. The processor chip according to claim 36, wherein at least some of the processor cores are reconfigurable in at least one of function and interconnection.

38. The processor chip according to claim 36, wherein the each of the at least some of the processor cores is reconfigurable in at least one of its function and its interconnection as defined by the instructions and on a hardware level by changing its active circuitry paths.

42. The processor chip according to claim 38, wherein the changing of the active circuitry paths is performed using a switching device.