Mode-based castout destination selection

• US 8,312,220 B2
• Filed: 04/09/2009
• Issued: 11/13/2012
• Est. Priority Date: 04/09/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Guthrie, Guy L., Helterhoff, Harmony L., Starke, William J., Williams, Phillip G., Stuecheli, Jeffrey A.
• Primary Examiner(s): Choe, Yong
• Application Number:
  US12/420,933
• Publication Number:
  US 20100262783A1
• Time in Patent Office: 1,314 Days
• Field of Search: 711/122, 711/133, 711/129
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/12 Replacement control

Abstract

In response to a data request of a first of a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and determines whether a mode is set. If not, the first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and indicating that a lower level cache is the intended destination. If the mode is set, the first processing unit issues a castout command with an alternative intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held elsewhere in the data processing system. The mode can be set to inhibit castouts to system memory, for example, for testing.

Claims

1. A method of data processing in a data processing system including a system memory and an interconnect fabric coupled to plurality of processing units each including a respective processor core and associated upper and lower level caches, said method comprising:

in response to a data request of the processor core of a first processing unit among the plurality of processing units;

selecting a victim cache line to be castout from a first lower level cache of the first processing unit;

determining as candidates for an intended destination of the victim cache line;

a second lower level cache selected from a first set containing exclusively lower level caches in the first processing unit; and

a third lower level cache selected from a second set of lower level caches including at least one lower level cache within one of the plurality of processing units other than the first processing unit, wherein all of the first, second and third lower level caches are at a same level of cache hierarchy;

determining whether a mode is set for the first processing unit;

selecting the second lower level cache as the intended destination if the mode is set, and if not, selecting the third lower level cache as the intended destination;

the first processing unit issuing a lateral castout (LCO) command on the interconnect fabric, wherein the LCO command identifies the victim cache line to be castout from the first lower level cache of the first processing unit and indicates the selected intended destination of the victim cache line; and

in response to a coherence response to the LCO command indicating success of the LCO command, removing the victim cache line from the first lower level cache of the first processing unit and holding the victim cache line elsewhere in the data processing system.

2. The method of claim 1, wherein the first, second and third lower level caches are victim caches, and wherein the first processing unit performs the selecting and removing steps.

3. The method of claim 1, wherein:

the method further comprises;

installing each of a plurality of cache lines in a congruence class of the first lower level cache and recording, in the first lower level cache, an access chronology for the plurality of cache lines and a respective membership of each of the plurality of cache lines in one of a plurality of classes including at least a first class and a second class, wherein the first class includes one or more cache lines of the congruence class more likely to be accessed by a first processor core of the first processing unit than one or more cache lines of the congruence class in the second class, wherein the membership of the plurality of cache lines in the plurality of classes is dependent on a type of access made to each of the plurality of cache lines and is independent of the access chronology of the plurality of cache lines; and

selecting the victim cache line includes selecting the victim cache line from among one or more cache lines in the second class while excluding one or more cache lines in the first class from the selection.

4. The method of claim 1, wherein holding the victim cache line elsewhere in the data processing system comprises:

in response to receipt of the LCO command, the lower level cache of a second processing unit among the plurality of processing units accepting the LCO command and holding the victim cache line.

5. The method of claim 1, wherein:

the alternative intended destination is system memory; and

the method further comprises in inhibiting all castout commands indicating system memory as an intended destination if the mode is set.

6. A data processing system, comprising:

an interconnect fabric; and

a plurality of processing units coupled to the interconnect fabric, the plurality of processing units each including a respective processor core and associated upper and lower level caches, wherein the plurality of processing units includes at least first, second and third processing units;

wherein the first processing unit, responsive to a data request;

selects a victim cache line to be castout from a first lower level cache of the first processing unit;

determines as candidates for an intended destination of the victim cache line;

a second lower level cache selected from a first set containing exclusively lower level caches in the first processing unit; and

a third lower level cache selected from a second set of lower level caches including at least one lower level cache within one of the plurality of processing units other than the first processing unit, wherein all of the first, second and third lower level caches are at a same level of cache hierarchy;

and determines whether a mode is set for the first processing unit;

selects the second lower level cache as the intended destination if the mode is set, and if not, selects the third lower level cache as the intended destination;

wherein the first processing unit issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the lower level cache of the first processing unit and indicating the selected intended destination of the victim cache line;

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from first lower level cache and the victim cache line is held elsewhere in the data processing system.

7. The data processing system of claim 6, wherein the first, second and third lower level caches are victim caches.

8. The data processing system of claim 6, wherein:

the first processing unit installs each of a plurality of cache lines in a congruence class of the first lower level cache and records, in the first lower level cache, an access chronology for the plurality of cache lines and a respective membership of each of the plurality of cache lines in one of a plurality of classes including at least a first class and a second class, wherein the first class includes one or more cache lines of the congruence class more likely to be accessed by a first processor core of the first processing unit than one or more cache lines of the congruence class in the second class, wherein the membership of the plurality of cache lines in the plurality of classes is dependent on a type of access made to each of the plurality of cache lines and is independent of the access chronology of the plurality of cache lines; and

the first processing unit selects the victim cache line from among one or more cache lines in the second class while excluding one or more cache lines in the first class from the selection.

9. The data processing system of claim 6, wherein, responsive to receipt of the LCO command, the lower level cache of the second processing unit accepts the LCO command and holds the victim cache line.

10. The data processing system of claim 6, wherein:

the alternative intended destination is system memory; and

the first processing unit inhibits all castout commands of the first processing unit that indicate system memory as an intended destination if the mode is set.

11. A processing unit for a data processing system including a plurality of processing units coupled by an interconnect fabric, the plurality of processing units including the processing unit as a first processing unit and additional second and third processing units, said first processing unit comprising:

at least a first processor core and associated first upper and first lower level caches;

wherein the first processing unit, responsive to a data request;

selects a victim cache line to be castout from the first lower level cache;

determines as candidates for an intended destination of the victim cache line;

a second lower level cache selected from a first set containing exclusively lower level caches in the first processing unit; and

a third lower level cache selected from a second set of lower level caches including at least one lower level cache within one of the plurality of processing units other than the first processing unit, wherein all of the first, second and third lower level caches are at a same level of cache hierarchy;

determines whether a mode is set for the first processing unit;

selects the second lower level cache as the intended destination if the mode is set, and if not, selects the third lower level cache as the intended destination;

wherein the first processing unit issues a lateral castout (LCO) command on the interconnect fabric, the LCO command identifying the victim cache line to be castout from the lower level cache of the first processing unit and indicating the selected intended destination of the victim cache line; and

wherein responsive to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from the first lower level cache and the victim cache line is held elsewhere in the data processing system.

12. The processing unit of claim 11, wherein:

each of the first, second and third lower level caches is a victim cache; and

the processing unit is a single integrated circuit chip.

13. The processing unit of claim 11, wherein, responsive to receipt of the LCO command, the lower level cache of the second processing unit accepts the LCO command and holds the victim cache line.

14. The processing unit of claim 11, wherein:

the alternative intended destination is system memory; and

the first processing unit inhibits all castout commands of the first processing unit that indicate system memory as an intended destination if the mode is set.