Serial buffer to support request packets with out of order response packets

• US 8,312,241 B2
• Filed: 03/06/2008
• Issued: 11/13/2012
• Est. Priority Date: 03/06/2008
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Wang, Chi-Lie, Mo, Jason Z.
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): SADLER, NATHAN
• Application Number:
  US12/043,943
• Publication Number:
  US 20090228630A1
• Time in Patent Office: 1,713 Days
• Field of Search: None
• US Class Current: 711/170
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9036 Common buffer combined with individual queues
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools

Abstract

Within a serial buffer, request packets are written to available memory blocks of a memory buffer, which are identified by a free buffer pointer list. When a request packet is written to a memory block, the memory block is removed from the free buffer pointer list, and added to a used buffer pointer list. Memory blocks in the used buffer pointer list are read, thereby transmitting the associated request packets from the serial buffer. When a request packet is read from a memory block, the memory block is removed from the used buffer pointer list and added to a request buffer pointer list. If a corresponding response packet is received within a timeout period, the memory block is transferred from the request buffer pointer list to the free buffer pointer list. Otherwise, the memory block is transferred from the request buffer pointer list to the used buffer pointer list.

Claims

1. A serial buffer comprising:

a buffer memory having a plurality of memory blocks, wherein the number of memory blocks is represented by an integer, N, and wherein each of the N memory blocks has corresponding unique memory block address;

a free buffer pointer list that includes N free buffer pointer entries, each storing a free buffer address that corresponds with the memory block address of a corresponding one of the N memory blocks, and each storing a first valid indicator that indicates whether the corresponding one of the N memory blocks is available to store a request packet;

a used buffer pointer list that includes N used buffer pointer entries, each storing a used buffer address that corresponds with the memory block address of a corresponding one of the N memory blocks, and each storing a second valid indicator that indicates whether the corresponding one of the N memory blocks stores a request packet to be transmitted out of the serial buffer; and

a request buffer pointer list that includes N request buffer pointer entries, each storing a request buffer address that corresponds with the memory block address of a corresponding one of the N memory blocks, and each storing a third valid indicator that indicates whether a request packet has been transmitted out of the serial buffer from the corresponding one of the N memory blocks, and a corresponding response is expected.

2. The serial buffer of claim 1, further comprising one or more queues that load request packets into the memory blocks of the buffer memory, wherein each of the request packets is loaded into a corresponding one of the memory blocks of the buffer memory.

3. The serial buffer of claim 1, wherein the expected corresponding response comprises a response packet received by the serial buffer or an indication that a timeout period has expired.

4. The serial buffer of claim 1, wherein the free buffer addresses are identical to the memory block addresses.

5. The serial buffer of claim 4, wherein the used buffer addresses are identical to the memory block addresses.

6. The serial buffer of claim 5, wherein the request buffer addresses are identical to the memory block addresses.

7. The serial buffer of claim 1, further comprising write control logic coupled to the free buffer pointer list, wherein the write control logic determines whether at least one of the first valid indicators indicates that one of the memory blocks is available to store a request packet.

8. The serial buffer of claim 1, further comprising request control circuit that reads request packets only from memory blocks identified by the used buffer pointer list as storing request packets to be transmitted out of the serial buffer.

9. The serial buffer of claim 8, further comprising a request timeout timer associated with each of the memory blocks, wherein the request control circuit starts the request timeout timer associated with a memory block upon reading a request packet from the memory block.

10. The serial buffer of claim 9, further comprising a response handler that stops the timeout timer upon receiving a response packet associated with the request packet read from the memory block.

11. The serial buffer of claim 10, wherein the request control circuit re-reads the request packet from the memory block upon detecting that the associated request timeout timer has expired.

12. The serial buffer of claim 1, further comprising request control circuit coupled to the used buffer pointer list and the buffer memory, wherein the request control circuit determines that one of the second valid indicators indicates that the corresponding one of the N memory blocks stores a request packet to be transmitted out of the serial buffer, and in response, retrieves the corresponding used buffer address from the used buffer pointer list, retrieves the request packet from the corresponding one of the N memory blocks using the retrieved used buffer address, and appends the retrieved used buffer address to the request packet.

13. The serial buffer of claim 1, further comprising response handler logic that identifies response packets received by the serial buffer in response to request packets read from the memory buffer.

14. The serial buffer of claim 1, wherein each of the memory blocks has a capacity equal to a maximum request packet size.

15. A method of operating a serial buffer comprising:

defining a plurality of memory blocks in a buffer memory, wherein the number of memory blocks is represented by an integer, N, and wherein each of the N memory blocks has corresponding unique memory block address;

maintaining a first list of each of the memory blocks available to store a request packet, the first list having N free buffer pointer entries, each including a free buffer address that corresponds with the memory block address of a corresponding one of the N memory blocks, and a first valid indicator that indicates whether the corresponding one of the memory blocks is available to store a request packet;

maintaining a second list of each of the memory blocks that stores a request packet to be transferred out of the serial buffer, the second list having N used buffer pointer entries, each including a used buffer address that corresponds with the memory block address of a corresponding one of the N memory blocks, and a second valid indicator that indicates whether the corresponding one of the N memory blocks stores a request packet to be transferred out of the serial buffer; and

maintaining a third list of each of the memory blocks that stores a request packet that has been transferred out of the serial buffer, but has not yet received an expected corresponding response, the third list having N request buffer pointer entries, each including a request buffer address that corresponds with the memory block address of a corresponding one of the N memory blocks, and a third valid indicator that indicates whether a request packet has been transferred out of the serial buffer from the corresponding one of the memory blocks, and a corresponding response is expected.

16. The method of claim 15, further comprising writing request packets only to memory blocks in the first list.

17. The method of claim 15, further comprising reading request packets only from memory blocks in the second list.

18. The method of claim 15, further comprising transferring a memory block from the first list to the second list in response to writing a request packet to the memory block.

19. The method of claim 15, further comprising transferring a memory block from the second list to the third list in response to reading a request packet from the memory block.

20. The method of claim 15, further comprising transferring a memory block from the third list to the first list in response to receiving a response packet associated with a request packet read from the memory block.