Input output access controller

• US 8,312,292 B2
• Filed: 07/31/2008
• Issued: 11/13/2012
• Est. Priority Date: 07/31/2007
• Status: Active Grant

• Current Assignee: ViaSat Incorporated
• Original Assignee: ViaSat Incorporated
• Inventors: Owens, John R., Andolina, John C., Shanken, Stuart N., Quintana, Richard L.
• Primary Examiner(s): THIAW, CATHERINE B
• Application Number:
  US12/184,079
• Publication Number:
  US 20090037631A1
• Time in Patent Office: 1,566 Days
• Field of Search: 713/189, 726/1, 709223-226, 711/100, 711/163
• US Class Current: 713/189
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 2221/2113 Multi-level security, e.g. mandatory access control
• CPC Class Codes: H04L 63/0485 Networking architectures for enhanced packet encryption processing, e.g. offloading of IPsec packet processing or efficient security association look-up
• CPC Class Codes: H04L 63/105 Multiple levels of security

Abstract

A device for high-assurance processing is disclosed. A processing circuit uses an access controller to assure that the processing circuit operates properly. The processing circuit runs software programs and is programmable. The access controller is programmable, but not programmable by the processing circuit. Peripherals or segments of the address space of the processing circuit is regulated. In a particular state, the peripherals that are available are regulated by the access controller. In some embodiments, the transition from state-to-state can also be regulated by the access controller.

Claims

1. A cryptographic device for processing classified information having a plurality of different classification levels, the cryptographic device comprising:

a processing circuit configured to;

access a plurality of peripherals, and

execute software programs;

an access controller, communicatively coupled to the processing circuit and configured to;

access a plurality of rules which the access controller applies for a plurality of states of the processing circuit;

regulate which of the plurality of states the processing circuit is allowed to transition to from each of the plurality of states, based on the plurality of rules, and

take or request remedial action when at least one of the plurality of rules is violated while the processing circuit is in one of the plurality of states;

wherein;

the plurality of rules specify, for each of the plurality of states;

which of the plurality of peripherals are allowed to be accessed by the processing circuit,

which operations are allowed to be performed by the processing circuit with each of the plurality of peripherals accessible to the processing circuit, the operations including at least one of read, write, or read and write, and

which of the plurality of states the processing circuit is allowed to transition to;

the plurality of rules are not fixed;

the plurality of rules may be changed, but cannot be changed;

by the processing circuit, or

during operation of the cryptographic device;

the access controller is not programmable by the processing circuit; and

the plurality of states comprise;

an idle state;

at least one operational state capable of being transitioned to from the idle state; and

a clean-up state during which data is purged from memory, the clean-up state capable of being transitioned to by the processing circuit at least once after the processing circuit transitions from the at least one operational state and before the processing circuit transitions back to the idle state.

2. The cryptographic device for processing classified information having the plurality of different classification levels as recited in claim 1, wherein each peripheral is defined by an address range within address space of the processing circuit.

3. The cryptographic device for processing classified information having the plurality of different classification levels as recited in claim 1, wherein used portions of an address space of the processing circuit are divided among the plurality of peripherals.

4. The cryptographic device for processing classified information having the plurality of different classification levels as recited in claim 1, wherein the plurality of rules limits a first state to transitioning to a second state.

5. The cryptographic device for processing classified information having the plurality of different classification levels as recited in claim 1, wherein the plurality of rules limits a first state from transitioning to a second state.

6. The cryptographic device for processing classified information having the plurality of different classification levels as recited in claim 1, wherein:

the plurality of rules limits a first state to an address range of a first peripheral, and

the first peripheral is one of the plurality of peripherals.

7. The cryptographic device for processing classified information having the plurality of different classification levels as recited in claim 1, wherein violation of one of the plurality of rules interrupts normal operation of the processing circuit.

8. The cryptographic device for processing classified information having the plurality of different classification levels as recited in claim 1,

wherein:

the plurality of peripherals comprises a first peripheral and a second peripheral,

the first peripheral is limited to a first classification level associated with a first state,

the second peripheral is limited to a second classification level associated with a second state, and

data from the first classification level is kept separate from data from the second classification level using the plurality of rules.

9. A high-security device for processing information, the high-security device comprising:

a processing circuit configured to;

access a plurality of peripherals, and

execute software programs

an access controller to prevent unauthorized use of a plurality of address ranges, communicatively coupled to the processing circuit and configured to;

access a plurality of rules which the access controller applies for a plurality of states of the processing circuit;

regulate which of the plurality of states the processing circuit is allowed to transition to from each of the plurality of states, based on the plurality of rules, and

take or request remedial action when at least one of the plurality of rules is violated while the processing circuit is in one of the plurality of states;

wherein;

the plurality of rules specify, for each of the plurality of states;

which of the plurality of peripherals are allowed to be accessed by the processing circuit,

which operations are allowed to be performed by the processing circuit with each of the plurality of peripherals accessible to the processing circuit, the operations including at least one of read, write, or read and write, and

which of the plurality of states the processing circuit is allowed to transition to;

the access controller is not programmable by the processing circuit;

the plurality of rules may be changed, but cannot be changed;

by the processing circuit or

during operation of the high-security device; and

the plurality of states comprise;

an idle state;

at least one operational state capable of being transitioned to from the idle state; and

a clean-up state during which data is purged from memory, the clean-up state capable of being transitioned to by the processing circuit at least once after the processing circuit transitions from the at least one operational state and before the processing circuit transitions back to the idle state.

10. The high-security device for processing information as recited in claim 9, wherein the access controller is a programmable circuit customized during design to incorporate the plurality of rules.

11. The high-security device for processing information as recited in claim 9, wherein the high-security device processes classified information through the plurality of rules to enforce data separation between a plurality of classification levels.

12. The high-security device for processing information as recited in claim 9, wherein each peripheral is defined by an address range within address space of the processing circuit.

13. The high-security device for processing information as recited in claim 9, wherein the plurality of rules limits a first state to transitioning to a second state.

14. The high-security device for processing information as recited in claim 9, wherein the plurality of rules limits a first state from transitioning to a second state.

15. The high-security device for processing information as recited in claim 9, wherein violation of one of the plurality of rules interrupts normal operation of the processing circuit.

16. The high-security device for processing information as recited in claim 9, wherein the processing circuit communicates the next state to the access controller.