Methods and devices for treating and processing data
DC CAFCFirst Claim
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1. A method of operating a system comprising a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, the tasks including at least one task having a first complexity and at least one task of less complexity than the first complexity, the method comprising:
- assigning the tasks for processing in a multiplexed manner such that the tasks are independent from each other, wherein certain of said elements are operational and process data only in case of requirement;
temporarily using one or more elements, having a workload due to an assignment of one or more of the tasks of less complexity than the first complexity, in a manner other than that which is for performing the one or more of the tasks of less complexity than the first complexity, the temporarily using being by temporarily assigning to the elements one or more different tasks; and
down-clocking currently unused data processing elements, such that the currently unused data processing elements are supplied with a clock rate maximally serving the preservation of memory contents.
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Abstract
A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.
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Citations
44 Claims
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1. A method of operating a system comprising a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, the tasks including at least one task having a first complexity and at least one task of less complexity than the first complexity, the method comprising:
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assigning the tasks for processing in a multiplexed manner such that the tasks are independent from each other, wherein certain of said elements are operational and process data only in case of requirement; temporarily using one or more elements, having a workload due to an assignment of one or more of the tasks of less complexity than the first complexity, in a manner other than that which is for performing the one or more of the tasks of less complexity than the first complexity, the temporarily using being by temporarily assigning to the elements one or more different tasks; and down-clocking currently unused data processing elements, such that the currently unused data processing elements are supplied with a clock rate maximally serving the preservation of memory contents. - View Dependent Claims (2)
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3. A method of operating a system having a plurality of data processing elements adapted for programmably processing sequences, to which tasks are assigned, and which are operable at different clock frequencies, the method comprising:
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grouping, by execution of software for managing distribution of code, a plurality of subsets of processing elements into processing element groups; effecting a plurality of temperature measurements in different regions of the system; and based on the temperature measurement, a control circuit modifying clock rates of the plurality of subsets of processing elements, wherein the clock rates set in the modifying step are set on a processing element group basis. - View Dependent Claims (4, 5)
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6. A processor device, comprising:
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a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, each of the data processing elements having at least one Arithmetic Logic Unit, and at least some of the data processing elements being adapted to operate at different clock frequencies that are adapted locally depending on a plurality of temperature measurements at different regions of the processor device; wherein a plurality of subsets of the data processing elements are grouped, by execution of software for managing distribution of code, into processing element groups, and the clock frequencies set for the data processing elements responsive to the temperature measurements are set on a processing element group basis, so that, for each of the groups, the clock frequency of the data processing elements of the group are modified in a same manner. - View Dependent Claims (7)
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8. A processor device, comprising
a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, each of the data processing elements having at least one Arithmetic Logic Unit; - and
at least one bus system at least one of (a) interconnecting at least some of the data processing elements and (b) connecting at least some of the data processing elements with at least one of peripherals and external memory; wherein; each of at least some of the data processing elements is capable of operating at a clock frequency different than at least one other of the data processing elements; and the processor device is adapted for reducing clock frequencies of the data processing elements in response to a determination that a power reserve of a battery is below a predetermined threshold. - View Dependent Claims (9, 11, 15, 18, 19, 20, 25, 26, 28, 32, 35, 36, 37)
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10. A processor device, comprising:
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a plurality of data processing elements; and a software adapted to be executed to (a) manage distribution of code sections, each code section to be executed by a respective group of a subset of the plurality of data processing elements, and (b) assign to each of the code sections a respective clock frequency, the group of data processing elements executing the respective code sections at the respective clock frequencies. - View Dependent Claims (13, 14, 16, 17, 27, 30, 31, 33, 34, 44)
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12. A processor device, comprising:
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a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, each of the data processing elements having at least one Arithmetic Logic Unit; and at least one bus system at least one of (a) interconnecting at least some of the data processing elements and (b) connecting at least some of the data processing elements with at least one of peripherals and external memory; wherein; each of at least some of the data processing elements is capable of operating at a clock frequency different than at least one other of the data processing elements; the clock frequency of each of the data processing elements is at least determinable by a state of the processing device; and the clock frequency for at least some of the data processing elements is set in accordance with a supply voltage. - View Dependent Claims (29)
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21. A processor device, comprising:
a plurality of data processing elements adapted such that, in response to a state in which the plurality of data processing elements are waiting for an input from an external element, at least one of the data processing elements enters a first sleep mode at a first clock frequency and the remaining data processing elements enter a second sleep mode at a second clock frequency that is slower than the first clock frequency;
wherein the at least one of the data processing elements triggers the plurality of data processing elements to wake up from the sleep modes and operate at a third clock frequency that is faster than the first and second clock frequencies in response to receipt by the at least one data processing element of the input.- View Dependent Claims (22, 38, 39)
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23. A processor device, comprising:
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a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, each of the data processing elements having at least one Arithmetic Logic Unit; and at least one bus system at least one of (a) interconnecting at least some of the data processing elements and (b) connecting at least some of the data processing elements with at least one of peripherals and external memory; wherein; each of at least some of the data processing elements is capable of operating at a clock frequency different than at least one other of the data processing elements; the clock frequency of each of the data processing elements is at least determinable by a state of the processing device; and the clock frequency of at least some of the data processing elements is determined by a fill level of at least one of an input data buffer and an output data buffer. - View Dependent Claims (40)
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24. A processor device, comprising:
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a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, each of the data processing elements having at least one Arithmetic Logic Unit; and at least one bus system at least one of (a) interconnecting at least some of the data processing elements and (b) connecting at least some of the data processing elements with at least one of peripherals and external memory; wherein; each of at least some of the data processing elements is capable of operating at a clock frequency different than at least one other of the data processing elements; the clock frequency of each of the data processing elements is at least determinable by a state of the processing device; and the clock frequency of at least some of the data processing elements is set based on whether data is determined to be available. - View Dependent Claims (41)
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42. A processor device comprising:
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a plurality of data processing elements that are dynamically grouped into a plurality of groups of subsets of the plurality of data processing elements during runtime, such that a group to which one or more of the plurality of data processing elements is assigned changes during runtime; a temperature measuring element; and a clock frequency control circuit that is adapted for independently setting respective clock frequencies of the data processing elements on a group by group basis according to a grouping prevailing when the setting is performed. - View Dependent Claims (43)
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Specification