Methods and devices for treating and processing data

• US 8,312,301 B2
• Filed: 09/30/2009
• Issued: 11/13/2012
• Est. Priority Date: 03/05/2001
• Status: Expired due to Term

• Current Assignee: PACT XPP Schweiz AG
• Original Assignee: Martin Vorbach, Volker Baumgarte
• Inventors: Vorbach, Martin, Baumgarte, Volker
• Primary Examiner(s): Elamin, M
• Application Number:
  US12/570,984
• Publication Number:
  US 20100023796A1
• Time in Patent Office: 1,140 Days
• Field of Search: 713/300, 713/310, 713320-324, 713/330, 713/340
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Claims

1. A method of operating a system comprising a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, the tasks including at least one task having a first complexity and at least one task of less complexity than the first complexity, the method comprising:

assigning the tasks for processing in a multiplexed manner such that the tasks are independent from each other, wherein certain of said elements are operational and process data only in case of requirement;

temporarily using one or more elements, having a workload due to an assignment of one or more of the tasks of less complexity than the first complexity, in a manner other than that which is for performing the one or more of the tasks of less complexity than the first complexity, the temporarily using being by temporarily assigning to the elements one or more different tasks; and

down-clocking currently unused data processing elements, such that the currently unused data processing elements are supplied with a clock rate maximally serving the preservation of memory contents.

2. The method according to claim 1, wherein the down-clocking depends on the amount of data to be processed.

3. A method of operating a system having a plurality of data processing elements adapted for programmably processing sequences, to which tasks are assigned, and which are operable at different clock frequencies, the method comprising:

grouping, by execution of software for managing distribution of code, a plurality of subsets of processing elements into processing element groups;

effecting a plurality of temperature measurements in different regions of the system; and

based on the temperature measurement, a control circuit modifying clock rates of the plurality of subsets of processing elements, wherein the clock rates set in the modifying step are set on a processing element group basis.

4. The method according to claim 3, wherein the system is an integrated circuit.

5. The method according to claim 4, wherein the integrated circuit is a processor.

6. A processor device, comprising:

a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, each of the data processing elements having at least one Arithmetic Logic Unit, and at least some of the data processing elements being adapted to operate at different clock frequencies that are adapted locally depending on a plurality of temperature measurements at different regions of the processor device;

wherein a plurality of subsets of the data processing elements are grouped, by execution of software for managing distribution of code, into processing element groups, and the clock frequencies set for the data processing elements responsive to the temperature measurements are set on a processing element group basis, so that, for each of the groups, the clock frequency of the data processing elements of the group are modified in a same manner.

7. The processor device according to claim any one of claims 6, wherein the processor device is an integrated circuit.

8. A processor device, comprising

a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, each of the data processing elements having at least one Arithmetic Logic Unit;

and

at least one bus system at least one of (a) interconnecting at least some of the data processing elements and (b) connecting at least some of the data processing elements with at least one of peripherals and external memory;

wherein;

each of at least some of the data processing elements is capable of operating at a clock frequency different than at least one other of the data processing elements; and

the processor device is adapted for reducing clock frequencies of the data processing elements in response to a determination that a power reserve of a battery is below a predetermined threshold.

9. The processor device according to claim 8, wherein at least some of the data processing elements have at least one locally connected memory for storing processing data.

11. The processor device according to claim 8, wherein the clock frequency for at least some of the data processing elements is determined by at least one other of the data processing elements.

15. The processor device according to claim 8, wherein a power supply voltage of each of at least some of the data processing elements is set depending on the clock frequency of the data processing elements.

18. The processor device according to claim 8, wherein a clock frequency of at least one of the data processing elements is reduced dynamically for preventing overheating of a chip.

19. The processor device according to claim 18, wherein the clock frequency is determined in response to a temperature sensor.

20. The processor device according to claim 8, wherein a frequency of the bus system is set independently from the frequency of the processor elements.

25. The processor device according to claim 8, further comprising at least one central clock, wherein the clock frequency of each of at least some of the data processing elements is derived from the at least one central clock

26. The processor device according to claim 25, wherein at least some of the data processing elements have at least one locally connected memory for storing processing data.

28. The processor device according to claim 11, further comprising at least one central clock, wherein the clock frequency of each of at least some of the data processing elements is derived from the at least one central clock.

32. The processor device according to claim 25, wherein a power supply voltage of each of at least some of the data processing elements is set depending on the clock frequency of the data processing elements.

35. The processor device according to claim 25, wherein a clock frequency of at least one of the data processing elements is reduced dynamically for preventing overheating of a chip.

36. The processor device according to claim 35, wherein the clock frequency is determined in response to a temperature sensor.

37. The processor device according to claim 25, wherein a frequency of the bus system is set independently from the frequency of the processor elements.

10. A processor device, comprising:

a plurality of data processing elements; and

a software adapted to be executed to (a) manage distribution of code sections, each code section to be executed by a respective group of a subset of the plurality of data processing elements, and (b) assign to each of the code sections a respective clock frequency, the group of data processing elements executing the respective code sections at the respective clock frequencies.

13. The processor device according to any one of the claims 8, 10, and 11, further comprising:

an arrangement for individually defining a power supply for at least one of the data processing elements depending on the clock frequency of the at least one of the data processing elements.

14. The processor device according to any one of the claims 8, 10, and 11, further comprising:

an arrangement for disabling a clock of at least some data processing elements at runtime; and

an arrangement for individually defining a power supply for at least one of the processing elements depending on the clock frequency of the at least one of the data processing elements.

16. The processor device according to any one of the claims 8, 10, 11, 12, and 15, wherein different parameters jointly establish the clock frequency of at least one of the data processing elements.

17. The processor device according to any one of the claims 8, 10, 11, 12, and 15, further comprising:

an arrangement for disabling a clock of at least some data processing elements at runtime.

27. The processor device according to claim 10, further comprising at least one central clock, wherein the clock frequency of each of at least some of the data processing elements is derived from the at least one central clock.

30. The processor device according to claim 13, further comprising at least one central clock, wherein the clock frequency of each of at least some of the data processing elements is derived from the at least one central clock.

31. The processor device according to claim 14, further comprising at least one central clock, wherein the clock frequency of each of at least some of the data processing elements is derived from the at least one central clock.

33. The processor device according to claim 16, further comprising at least one central clock, wherein the clock frequency of each of at least some of the data processing elements is derived from the at least one central clock.

34. The processor device according to claim 17, further comprising at least one central clock, wherein the clock frequency of each of at least some of the data processing elements is derived from the at least one central clock.

44. The processor device according to claim 10, wherein the plurality of data processing elements are runtime configurable, and the code sections are configurations of respective groups of the plurality of data processing elements.

12. A processor device, comprising:

a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, each of the data processing elements having at least one Arithmetic Logic Unit; and

at least one bus system at least one of (a) interconnecting at least some of the data processing elements and (b) connecting at least some of the data processing elements with at least one of peripherals and external memory;

wherein;

each of at least some of the data processing elements is capable of operating at a clock frequency different than at least one other of the data processing elements;

the clock frequency of each of the data processing elements is at least determinable by a state of the processing device; and

the clock frequency for at least some of the data processing elements is set in accordance with a supply voltage.

29. The processor device according to claim 12, further comprising at least one central clock, wherein the clock frequency of each of at least some of the data processing elements is derived from the at least one central clock.

21. A processor device, comprising:

a plurality of data processing elements adapted such that, in response to a state in which the plurality of data processing elements are waiting for an input from an external element, at least one of the data processing elements enters a first sleep mode at a first clock frequency and the remaining data processing elements enter a second sleep mode at a second clock frequency that is slower than the first clock frequency;

wherein the at least one of the data processing elements triggers the plurality of data processing elements to wake up from the sleep modes and operate at a third clock frequency that is faster than the first and second clock frequencies in response to receipt by the at least one data processing element of the input.

22. The processor device according to claim 21, further comprising a power saving arrangement for reducing the power supply of least the data processing elements operating at the first and second clock frequencies.

38. The processor device according to claim 21, further comprising at least one central clock, wherein clock frequency of each of at least some of the data processing elements is derived from the at least one central clock.

39. The processor device according to claim 38, further comprising a power saving arrangement for reducing the power supply of least the data processing elements operating at the first and second clock frequencies.

23. A processor device, comprising:

a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, each of the data processing elements having at least one Arithmetic Logic Unit; and

at least one bus system at least one of (a) interconnecting at least some of the data processing elements and (b) connecting at least some of the data processing elements with at least one of peripherals and external memory;

wherein;

each of at least some of the data processing elements is capable of operating at a clock frequency different than at least one other of the data processing elements;

the clock frequency of each of the data processing elements is at least determinable by a state of the processing device; and

the clock frequency of at least some of the data processing elements is determined by a fill level of at least one of an input data buffer and an output data buffer.

40. The processor device according to claim 23, further comprising at least one central clock, wherein the clock frequency of each of at least some of the data processing elements is derived from the at least one central clock.

24. A processor device, comprising:

a plurality of data processing elements adapted for programmably processing sequences and to which tasks are assigned, each of the data processing elements having at least one Arithmetic Logic Unit; and

at least one bus system at least one of (a) interconnecting at least some of the data processing elements and (b) connecting at least some of the data processing elements with at least one of peripherals and external memory;

wherein;

each of at least some of the data processing elements is capable of operating at a clock frequency different than at least one other of the data processing elements;

the clock frequency of each of the data processing elements is at least determinable by a state of the processing device; and

the clock frequency of at least some of the data processing elements is set based on whether data is determined to be available.

41. The processor device according to claim 24, further comprising at least one central clock, wherein the clock frequency of each of at least some of the data processing elements is derived from the at least one central clock.

42. A processor device comprising:

a plurality of data processing elements that are dynamically grouped into a plurality of groups of subsets of the plurality of data processing elements during runtime, such that a group to which one or more of the plurality of data processing elements is assigned changes during runtime;

a temperature measuring element; and

a clock frequency control circuit that is adapted for independently setting respective clock frequencies of the data processing elements on a group by group basis according to a grouping prevailing when the setting is performed.

43. The processor device according to claim 42, wherein the data processing elements are runtime configurable data processing elements according to a plurality of configurations, wherein the configurations define the groupings of the data processing elements.