Information processing device, data transmitting device, and data transfer method of data transmitting device
First Claim
Patent Images
1. An information processing apparatus comprising:
- a data transmitting device that transmits data with N-bit width (N;
positive integer);
a data receiving device that receives the data with N-bit width; and
a system monitoring device connected to the data transmitting device and the data receiving device, whereinthe data transmitting device includesa first data-with-parity generating circuit that generates first data with parity in which a parity is added to first data with X-bit width (X;
positive integer satisfying N>
X) of the data with N-bit width;
a second data-with-parity generating circuit that generates second data with parity in which a parity is added to second data with (N−
X)-bit width of the data with N-bit width;
a first ECC generating circuit that generates first ECC data for the first data;
a second ECC generating circuit that generates second ECC data for the second data;
a selection-signal generating circuit that generates and outputs a first selection signal and a second selection signal based on a first or a second error notification signal for the first or the second data with parity received from the data receiving device;
a first selecting circuit that selects and outputs either one of the first data with parity and the second ECC data based on the first selection signal;
a second selecting circuit that selects and outputs either one of the first ECC data and the second data with parity based on the second selection signal; and
a data processing unit that degenerates the data with N-bit width to either the first data or the data with (N−
X)-bit width based on a data-width degeneration notification signal received from the system monitoring device, and outputs degenerated data, andthe data receiving device includesa first parity checking circuit that detects a parity error for the first data with parity and outputs the first error notification signal when an error occurs;
a second parity checking circuit that detects a parity error for the second data with parity and outputs the second error notification signal when an error occurs;
a first ECC correcting circuit that detects and corrects an ECC error for the first ECC data; and
a second ECC correcting circuit that detects and corrects an ECC error for the second ECC data.
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Abstract
A selection-signal generating circuit in an LSI being a transmission-side LSI, when a transmission error is detected on an A-side signal line and degeneration control is performed thereon, instructs a selector to select an input from an ECC generator in order to transmit data and ECC data for this data to be transmitted via the B-side signal line, via the A-side signal line. In this manner, the degenerated signal line is used to transmit the ECC data for transmission data to be transmitted via a signal line which is not degenerated.
10 Citations
8 Claims
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1. An information processing apparatus comprising:
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a data transmitting device that transmits data with N-bit width (N;
positive integer);a data receiving device that receives the data with N-bit width; and a system monitoring device connected to the data transmitting device and the data receiving device, wherein the data transmitting device includes a first data-with-parity generating circuit that generates first data with parity in which a parity is added to first data with X-bit width (X;
positive integer satisfying N>
X) of the data with N-bit width;a second data-with-parity generating circuit that generates second data with parity in which a parity is added to second data with (N−
X)-bit width of the data with N-bit width;a first ECC generating circuit that generates first ECC data for the first data; a second ECC generating circuit that generates second ECC data for the second data; a selection-signal generating circuit that generates and outputs a first selection signal and a second selection signal based on a first or a second error notification signal for the first or the second data with parity received from the data receiving device; a first selecting circuit that selects and outputs either one of the first data with parity and the second ECC data based on the first selection signal; a second selecting circuit that selects and outputs either one of the first ECC data and the second data with parity based on the second selection signal; and a data processing unit that degenerates the data with N-bit width to either the first data or the data with (N−
X)-bit width based on a data-width degeneration notification signal received from the system monitoring device, and outputs degenerated data, andthe data receiving device includes a first parity checking circuit that detects a parity error for the first data with parity and outputs the first error notification signal when an error occurs; a second parity checking circuit that detects a parity error for the second data with parity and outputs the second error notification signal when an error occurs; a first ECC correcting circuit that detects and corrects an ECC error for the first ECC data; and a second ECC correcting circuit that detects and corrects an ECC error for the second ECC data. - View Dependent Claims (2, 3)
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4. A data transmitting device for transmitting data with N-bit width to a data receiving device connected to a system monitoring device and that is connected to the system monitoring device, the data transmitting device comprising:
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a first data-with-parity generating circuit that generates first data with parity in which a parity is added to first data with X-bit width (X;
positive integer satisfying N>
X) of the data with N-bit width;a second data-with-parity generating circuit that generates second data with parity in which a parity is added to second data with (N−
X)-bit width of the data with N-bit width;a first ECC generating circuit that generates first ECC data for the first data; a second ECC generating circuit that generates second ECC data for the second data; a selection-signal generating circuit that generates and outputs a first selection signal and a second selection signal based on a first or a second error notification signal for the first or the second data with parity received from the data receiving device; a first selecting circuit that selects and outputs either one of the first data with parity and the second ECC data based on the first selection signal; a second selecting circuit that selects and outputs either one of the first ECC data and the second data with parity based on the second selection signal; and a data processing unit that degenerates the data with N-bit width to either the first data or the data with (N−
X)-bit width based on a data-width degeneration notification signal received from the system monitoring device, and outputs degenerated data. - View Dependent Claims (5)
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6. A data transfer method for a data transmitting device that transmits data with N-bit width to a data receiving device connected to a system monitoring device and that is connected to the system monitoring device, the data transfer method comprising:
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generating, by a first data-with-parity generating circuit, first data with parity in which a parity is added to first data with X-bit width (X;
positive integer satisfying N>
X) of the data with N-bit width;generating, by a second data-with-parity generating circuit, second data with parity in which a parity is added to second data with (N−
X)-bit width of the data with N-bit width;selecting and outputting the first data with parity by a first selecting circuit; selecting and outputting the second data with parity by a second selecting circuit; generating and outputting, by a selection-signal generating circuit, a first selection signal and a second selection signal based on a first or a second error notification signal for the first or the second data with parity received from the data receiving device; regenerating the first data with parity by a first data-with-parity generating circuit; regenerating the second data with parity by a second data-with-parity generating circuit; generating first ECC data for the first data by a first ECC generating circuit; generating second ECC data for the second data by a second ECC generating circuit; degenerating, by a data processing unit, the data with N-bit width to either the first data or the data with (N−
X)-bit width based on a data-width degeneration notification signal received from the system monitoring device, and outputting degenerated data;generating and outputting, by a selection-signal generating circuit, a first selection signal and a second selection signal based on a first or a second error notification signal for the first or the second data with parity received from the data receiving device; selecting and outputting, by a first selecting circuit, either one of the first data with parity and the second ECC data based on the first selection signal; and selecting and outputting, by a second selecting circuit, either one of the first ECC data and the second data with parity based on the second selection signal. - View Dependent Claims (7, 8)
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Specification
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Current AssigneeFujitsu Limited
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Original AssigneeFujitsu Limited
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InventorsItozawa, Shintaro, Nakayama, Hiroshi, Ichimiya, Junji
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Primary Examiner(s)Torres, Joseph D
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Application NumberUS12/926,690Publication NumberTime in Patent Office711 DaysField of Search714/751, 714/757, 714/774US Class Current714/751CPC Class CodesG06F 11/0724 in a multiprocessor or a mu...G06F 11/0763 by bit configuration check,...H04L 1/0009 by adapting the channel cod...H04L 1/0057 Block codes H04L1/0061, H04...H04L 1/007 Unequal error protection fo...H04L 25/14 Channel dividing arrangemen...
