Determining data transmission error and/or checking or confirming such error determinations
First Claim
1. A method of determining or confirming an error in transmitted data, comprising:
- receiving transmitted data and then partitioning the received data into a plurality of data lines each having a first fixed length, and a last line containing an error checking code calculated on said transmitted data;
when said last line is less than said first length, appending to the last line a pad vector that is dimensioned to make the last line, including the appended pad vector, the first length;
performing an error checking calculation on the plurality of data lines and on the last line including the error checking code and the pad vector to calculate an error checking result;
determining a state of the calculated error checking result; and
indicating an error or an absence of an error in the transmitted data based on the calculated error checking result.
2 Assignments
0 Petitions
Accused Products
Abstract
A data partitioning circuit partitions received data and an appended error checking code into a plurality of data lines having a fixed length and a last line. A vector selector inserts a pad vector after the appended error checking code when the last line is less than the first length and not equal to the first fixed length minus a length of the appended error checking code, and selects one of a plurality of error checking vectors, the pad vector having a length providing the last line with the first fixed length when appended thereafter, and the plurality of error checking vectors comprising an initial vector and an error checking code feedback vector. An error checking code calculation circuit performs error checking calculations on the plurality of data lines and the last line to generate an error checking result.
59 Citations
42 Claims
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1. A method of determining or confirming an error in transmitted data, comprising:
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receiving transmitted data and then partitioning the received data into a plurality of data lines each having a first fixed length, and a last line containing an error checking code calculated on said transmitted data; when said last line is less than said first length, appending to the last line a pad vector that is dimensioned to make the last line, including the appended pad vector, the first length; performing an error checking calculation on the plurality of data lines and on the last line including the error checking code and the pad vector to calculate an error checking result; determining a state of the calculated error checking result; and indicating an error or an absence of an error in the transmitted data based on the calculated error checking result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42)
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11. A circuit for determining a data transmission error and/or checking a data transmission error determination, comprising:
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a data partitioning circuit configured to receive transmitted data and an appended error checking code calculated on said transmitted data, and partition said received data and said appended error checking code into a plurality of data lines having a fixed length and a last line containing the appended error checking code; a vector selector configured to insert a pad vector after said appended error checking code when the last line is less than said first length and not equal to said first fixed length minus a length of said appended error checking code, and select one of a plurality of error checking vectors, the pad vector having a length providing said last line with said first fixed length when appended thereafter, and the plurality of error checking vectors comprising an initial vector and an error checking code feedback vector; and an error checking code calculation circuit configured to perform error checking calculations on the plurality of data lines and the last line to generate an error checking result; a logic circuit configured to indicate an error or an absence of an error in the transmitted data based on the calculated error checking result. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A receiver, comprising:
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a data partitioning circuit configured to receive transmitted data and an appended error checking code calculated on said transmitted data, and partition said received data and said appended error checking code into a plurality of data lines having a fixed length and a last line containing the appended error checking code; a vector selector configured to insert a pad vector after said appended error checking code when the last line is less than said first length and not equal to said first fixed length minus a length of said appended error checking code, and select one of a plurality of error checking vectors, the pad vector having a length providing said last line with said first fixed length when appended thereafter, and the plurality of error checking vectors comprising an initial vector and an error checking code feedback vector; an error checking code calculation circuit configured to perform error checking calculations on the plurality of data lines and the last line to generate an error checking result; a logic circuit configured to indicate an error or an absence of an error in the transmitted data based on the calculated error checking result; a processor in communication with said data partitioning circuit, configured to process said received data; and a clock recovery circuit configured to recover a clock signal from said received data. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A circuit for determining a data transmission error and/or confirming an error determination, comprising:
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means for receiving transmitted data and error checking code calculated thereon and appended thereto, and partitioning said received data and said appended error checking code into (i) a plurality of data lines having a fixed length, and (ii) a last line containing the appended error checking code; means for performing error checking calculations on the plurality of data lines to generate an error checking result; means for selecting one of a plurality of error checking vectors, said plurality of error checking vectors comprising an initial vector, an error checking code feedback vector, and a pad vector; means for inserting said pad vector after said appended error checking code when said received data comprises a remainder, said remainder having any length less than said first fixed length and not equal to said first fixed length minus a length of said appended error checking code, said pad vector having a length providing said last line with said first fixed length when appended thereto; and means for indicating an error or an absence of an error in the transmitted data based on the error checking result.
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Specification