Apparatus and methods for electrochemical processing of microfeature wafers

• US 8,313,631 B2
• Filed: 11/02/2010
• Issued: 11/20/2012
• Est. Priority Date: 01/29/2007
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: McHugh, Paul R., Wilson, Gregory J., Woodruff, Daniel J.
• Primary Examiner(s): VAN, LUAN V
• Application Number:
  US12/917,997
• Publication Number:
  US 20110042224A1
• Time in Patent Office: 749 Days
• Field of Search: 205/96, 205/97, 204/260, 204/272
• US Class Current: 205/96
• CPC Class Codes: C25D 17/001 Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
• CPC Class Codes: C25D 17/10 Electrodes , e.g. composition, counter electrode
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: C25F 3/30 of semiconducting materials

Abstract

Apparatus and methods for electrochemically processing microfeature wafers. The apparatus can have a vessel including a processing zone in which a microfeature wafer is positioned for electrochemical processing. The apparatus further includes at least one counter electrode in the vessel that can operate as an anode or a cathode depending upon the particular plating or electropolishing application. The apparatus further includes a supplementary electrode and a supplementary virtual electrode. The supplementary electrode is configured to operate independently from the counter electrode in the vessel, and it can be a thief electrode and/or a de-plating electrode depending upon the type of process. The supplementary electrode can further be used as another counter electrode during a portion of a plating cycle or polishing cycle. The supplementary virtual electrode is located in the processing zone, and it is configured to counteract an electric field offset relative to the wafer associated with an offset between the wafer and the counter electrode in the vessel when the wafer is in the processing zone.

Claims

1. A method for electrochemically processing a microfeature wafer, comprising:

holding a wafer in a wafer holder in a processing zone of a vessel;

establishing an electric field in a processing fluid in the vessel using the wafer, a counter electrode in the vessel, and a supplementary electrode spaced apart from the wafer holder;

wherein the supplementary electrode affects the electric field via a supplementary virtual electrode in the processing zone, and the supplementary electrode comprises an inclined annular ring oriented at a non-zero angle relative to the supplementary virtual electrode.

2. The method of claim 1 further including counteracting an offset of the electric field relative to the wafer associated with an offset between the wafer holder and the vessel by shaping the supplementary virtual electrode to have a first width at a first side of the wafer holder and a second width different than the first width at a second side of the wafer holder.

4. The method of claim 1 wherein the supplementary electrode is located above the processing zone, and further comprising plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

5. The method of claim 1 wherein the supplementary electrode is located above the counter electrode, and further comprising de-plating material using the supplementary electrode.

6. The method of claim 1 wherein the supplementary electrode is located above the processing zone, and further comprising de-plating material using the supplementary electrode.

7. The method of claim 1 wherein the vessel includes a member having an inner edge, a rim above the inner edge, and a perimeter, and wherein the supplementary electrode is located above the member at a radial position between the inner edge and the perimeter, and further comprising plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

8. The method of claim 7 further comprising shaping an electric field component using a supplementary virtual electrode having an aperture formed, at least in part, by the inner edge of the member, and further comprising plating onto the supplementary electrode to thieve material relative to a perimeter of the wafer.

9. The method of claim 1 with the supplementary virtual electrode comprising an aperture filled with processing fluid, further comprising compensating for misalignment between the wafer and the counter electrode by passing electric current through processing fluid in the aperture, and with the aperture formed, at least in part, by a portion of the vessel at the processing zone and a portion of the wafer holder.

10. The method of claim 7 further comprising establishing the electric field using a plurality of counter electrodes and operating the counter electrodes independently from each other and the supplementary electrode.

11. The method of claim 1 further comprising operating a plurality of counter electrodes independently from each other and the supplementary electrode.

3. The method of 1 wherein the supplementary electrode is located above the supplementary virtual electrode.