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Device fabrication

  • US 8,314,024 B2
  • Filed: 05/15/2009
  • Issued: 11/20/2012
  • Est. Priority Date: 12/19/2008
  • Status: Expired due to Fees
First Claim
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1. A method for device fabrication, comprising:

  • providing a trailing edge front-end-of-the-line (FEOL) circuitry fabrication technology configured for fabricating FEOL circuitry die on a base wafer at a first investment cost using capital assets that are substantially depreciated and selected for fabricating the FEOL circuitry die at a first cost per wafer; and

    providing a leading edge back-end-of-the-line (BEOL) memory fabrication technology configured for fabricating one or more BEOL memory layers directly on top of each FEOL circuitry die on the base wafer at a second investment cost that is greater than the first investment cost using capital assets having substantially no depreciation and selected for fabricating the one or more BEOL memory layers at a second cost per wafer that is greater than the first cost per wafer.

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