Device fabrication
First Claim
1. A method for device fabrication, comprising:
- providing a trailing edge front-end-of-the-line (FEOL) circuitry fabrication technology configured for fabricating FEOL circuitry die on a base wafer at a first investment cost using capital assets that are substantially depreciated and selected for fabricating the FEOL circuitry die at a first cost per wafer; and
providing a leading edge back-end-of-the-line (BEOL) memory fabrication technology configured for fabricating one or more BEOL memory layers directly on top of each FEOL circuitry die on the base wafer at a second investment cost that is greater than the first investment cost using capital assets having substantially no depreciation and selected for fabricating the one or more BEOL memory layers at a second cost per wafer that is greater than the first cost per wafer.
3 Assignments
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Accused Products
Abstract
Device fabrication is disclosed, including forming a first part of a device at a first fabrication facility as part of a front-end-of-the-line (FEOL) process, the first part of the device comprising a base wafer formed by FEOL processing, and subsequently performing one or more back-end-of-the-line (BEOL) processes at a second fabrication facility to form an IC, the one or more BEOL processes comprising finishing the forming of the device (e.g., an IC including memory) by depositing one or more memory layers on the base wafer. FEOL processing can be used to form active circuitry die (e.g., CMOS circuitry on a Si wafer) and BEOL processing can be used to form on top of each active circuitry die, one or more layers of cross-point memory arrays formed by thin film processing technologies that may or may not be compatible with or identical to some or all of the FEOL processes.
41 Citations
16 Claims
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1. A method for device fabrication, comprising:
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providing a trailing edge front-end-of-the-line (FEOL) circuitry fabrication technology configured for fabricating FEOL circuitry die on a base wafer at a first investment cost using capital assets that are substantially depreciated and selected for fabricating the FEOL circuitry die at a first cost per wafer; and providing a leading edge back-end-of-the-line (BEOL) memory fabrication technology configured for fabricating one or more BEOL memory layers directly on top of each FEOL circuitry die on the base wafer at a second investment cost that is greater than the first investment cost using capital assets having substantially no depreciation and selected for fabricating the one or more BEOL memory layers at a second cost per wafer that is greater than the first cost per wafer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification