Semiconductor device and method for manufacturing the same
First Claim
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1. A method for manufacturing a semiconductor device, comprising the steps of:
- forming, over a substrate, a source electrode and a drain electrode from a metal film anda channel layer from oxide semiconductor;
forming a gate insulating film over the source electrode, the drain electrode, and the channel layer;
forming a conductive film over the gate insulating filmcoating the conductive film with negative resist;
exposing the negative resist to light from a back of the substrate using the source electrode and the drain electrode as a mask;
removing the negative resist except for an exposed part of the negative resist;
forming a gate electrode by etching the conductive film using the exposed part as an etching mask;
forming a first interconnect from the metal film on the substrate together with the source electrode and the drain electrode;
exposing the negative resist to light from the back of the substrate using, as a mask, the first interconnect as well as the source electrode and the drain electrode;
exposing part of the negative resist just above the first interconnect to light from a front side of the substrate through a photo mask;
removing the negative resist except exposed part of the negative resist; and
forming a second interconnect together with the age electrode by etching the conductive film using the exposed part as an etching mask.
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Abstract
A method for manufacturing a thin film transistor (TFT) through a process including back exposure, in which oxide semiconductor is used for a channel layer; using an electrode over a substrate as a mask, negative resist is exposed to light from the back of the substrate; the negative resist except its exposed part is removed; and an electrode is shaped by etching a conductive film using the exposed part as an etching mask.
49 Citations
17 Claims
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1. A method for manufacturing a semiconductor device, comprising the steps of:
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forming, over a substrate, a source electrode and a drain electrode from a metal film and a channel layer from oxide semiconductor; forming a gate insulating film over the source electrode, the drain electrode, and the channel layer; forming a conductive film over the gate insulating film coating the conductive film with negative resist; exposing the negative resist to light from a back of the substrate using the source electrode and the drain electrode as a mask; removing the negative resist except for an exposed part of the negative resist; forming a gate electrode by etching the conductive film using the exposed part as an etching mask; forming a first interconnect from the metal film on the substrate together with the source electrode and the drain electrode; exposing the negative resist to light from the back of the substrate using, as a mask, the first interconnect as well as the source electrode and the drain electrode; exposing part of the negative resist just above the first interconnect to light from a front side of the substrate through a photo mask; removing the negative resist except exposed part of the negative resist; and forming a second interconnect together with the age electrode by etching the conductive film using the exposed part as an etching mask. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for manufacturing a semiconductor device, comprising the steps of:
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forming a gate electrode from a metal film over a substrate; forming a gate insulating film over the gate electrode and the substrate; forming a channel layer from oxide semiconductor over the gate insulating film; forming a conductive film over the channel layer; coating the conductive film with negative resist; exposing the negative resist to light from a back of the substrate using the gate electrode as a mask; removing the negative resist except for an exposed part of the negative resist; and forming a source electrode and a drain electrode by etching the conductive film using the exposed part as an etching mask; forming a first interconnect from the metal film on the substrate together with the gate electrode; exposing the negative resist to light from the back of the substrate using, as a mask, the first interconnect as well as the gate electrode; exposing part of the negative resist just above the first interconnect to light from a front side of the substrate through a photo mask; removing the negative resist except exposed part of the negative resist; and forming a second interconnect together with the source electrode and the drain electrode by etching the conductive film using the exposed part as an etching mask. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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17. A semiconductor device manufactured by:
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forming, over a substrate, a source electrode and a drain electrode from a metal film and a channel layer from oxide semiconductor; forming a gate insulating film over the source electrode, the drain electrode, and the channel layer; forming a conductive film over the gate insulating film; coating the conductive film with negative resist; exposing the negative resist to light from a back of the substrate using the source electrode and the drain electrode as a mask; removing the negative resist except for an exposed part of the negative resist; forming a gate electrode by etching the conductive film using the exposed part as an etching mask; forming a first interconnect from the metal film on the substrate together with the source electrode and the drain electrode; exposing the negative resist to light from the back of the substrate using, as a mask, the first interconnect as well as the source electrode and the drain electrode; exposing part of the negative resist just above the first interconnect to light from a front side of the substrate through a photo mask; removing the negative resist except exposed part of the negative resist; and forming a second interconnect together with the gate electrode by etching the conductive film using the exposed part as an etching mask.
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Specification
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Current AssigneeHitachi, Ltd.
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Original AssigneeHitachi, Ltd.
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InventorsKawamura, Tetsufumi, Uchiyama, Hiroyuki, Wakana, Hironori, Hatano, Mutsuko, Sato, Takeshi
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Primary Examiner(s)Stark, Jarrett
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Assistant Examiner(s)TOBERGTE, NICHOLAS J
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Application NumberUS12/838,451Publication NumberTime in Patent Office857 DaysField of Search438/299, 438/700, 438/708, 257/47US Class Current438/700CPC Class CodesH01L 29/7869 having a semiconductor body...
