Light emitting diode chip and method of fabricating the same

• US 8,314,440 B2
• Filed: 03/28/2011
• Issued: 11/20/2012
• Est. Priority Date: 12/24/2010
• Status: Active Grant

• Current Assignee: Seoul Semiconductor Co., Ltd.
• Original Assignee: Seoul Optodevice Company Limited (Seoul Semiconductor Co., Ltd.)
• Inventors: Kim, Jong Kyu, Shin, Jin Cheol, Lee, Sum Geun, Heo, Min Chan, Jin, Sang Ki, Lee, So Ra
• Primary Examiner(s): Sefer, A.
• Assistant Examiner(s): Yushin, Nikolay
• Application Number:
  US13/073,522
• Publication Number:
  US 20120161176A1
• Time in Patent Office: 603 Days
• Field of Search: 257/13, 257/98, 257/79, 257/E33.055, 257/99, 257/E33.001, 257/E33.067, 438/22, 438/27, 438/29
• US Class Current: 257/98
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/50 Wavelength conversion elements
• CPC Class Codes: H01L 33/60 Reflective elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Exemplary embodiments of the present invention provide light emitting diode (LED) chips and a method of fabricating the same. An LED chip according to an exemplary embodiment includes a substrate; a light emitting structure arranged on the substrate, and an alternating lamination bottom structure arranged under the substrate. The alternating lamination bottom structure includes a plurality of dielectric pairs, each of the dielectric pairs including a first material layer having a first refractive index and a second material layer having a second refractive index, the first refractive index being greater than the second refractive index.

Claims

1. A light emitting diode (LED) chip, comprising:

a substrate;

a light emitting structure arranged on the substrate, the light emitting structure comprising a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; and

an alternately laminated bottom structure disposed on the substrate and comprising dielectric pairs, each of the dielectric pairs comprising a first material layer having a first refractive index and a second material layer having a second refractive index, the first refractive index being greater than the second refractive index, the dielectric pairs comprising;

first dielectric pairs each comprising the first material layer and the second material layer, the first material layer and the second material layer each having an optical thickness less than λ

/4;

a second dielectric pair comprising the first material layer and the second material layer, one of the first material layer and the second material layer having an optical thickness less than λ

/4 and the other having an optical thickness greater than λ

/4; and

third dielectric pairs comprising the first material layer and the second material layer, each of the first material layer and the second material layer having an optical thickness greater than λ

/4,

wherein λ

is a central wavelength of the visible light range, and

wherein the first dielectric pairs are located closer to or farther from the substrate than the third dielectric pairs.

2. The LED chip of claim 1, wherein the second dielectric pair separates the first dielectric pairs and the third dielectric pairs.

3. The LED chip of claim 1, wherein at least half the first dielectric pairs are arranged closer to the substrate than the second dielectric pair, at least half the third dielectric pairs are located farther from the substrate than the second dielectric pair.

4. The LED chip of claim 1, wherein at least 80% of the first dielectric pairs are located closer to the substrate than the second dielectric pair, and at least 80% of the third dielectric pairs are located farther from the substrate than the second dielectric pair.

5. The LED chip of claim 1, wherein the first dielectric pairs are arranged closer to the substrate than the third dielectric pairs.

6. The LED chip of claim 1, wherein at least half the third dielectric pairs are arranged closer to the substrate than the second dielectric pair, and at least half the first dielectric pairs are arranged farther from the substrate than the second dielectric pair.

7. The LED chip of claim 1, wherein the first dielectric pairs are located farther from the substrate than the third dielectric pairs.

8. A light emitting diode (LED) chip, comprising:

a substrate;

a light emitting structure arranged on the substrate, the light emitting structure comprising a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer;

an alternately laminated bottom structure disposed on the substrate and comprising dielectric pairs, each of the dielectric pairs comprising a first material layer having a first refractive index and a second material layer having a second refractive index, the first refractive index being greater than the second refractive index, the dielectric pairs comprising;

first dielectric pairs each comprising the first material layer and the second material layer, the first material layer and the second material layer each having an optical thickness less than λ

/4;

a second dielectric pair comprising the first material layer and the second material layer, one of the first material layer and the second material layer having an optical thickness less than λ

/4 and the other having an optical thickness greater than λ

/4; and

third dielectric pairs comprising the first material layer and the second material layer, each of the first material layer and the second material layer having an optical thickness greater than λ

/4,

wherein λ

is a central wavelength of the visible light range; and

an alternately laminated top structure arranged on the light emitting structure, the alternately laminated top structure configured to transmit light generated in the active layer and to reflect light within at least a portion of the visible light spectrum, the reflected light having a longer wavelength than light generated in the active region.

9. The LED chip of claim 8, wherein the alternately laminated top structure has a transmittance of at least 90% with respect to light generated in the active layer.

10. The LED chip of claim 9, further comprising:

an electrode pad electrically connected to the second conductivity type semiconductor layer; and

an alternately laminated under structure disposed between the second conductivity type semiconductor layer and the electrode pad and configured to reflect light generated in the active layer.

11. The LED chip of claim 10, further comprising a metal reflector disposed on the alternately laminated bottom structure.

12. The LED chip of claim 11, wherein the alternately laminated bottom structure or a combination of the alternately laminated bottom structure and the metal reflector has a reflectance of at least 90%, with respect to light generated in the active layer and that enters the alternately laminated bottom structure at an angle of incidence of from 0 degrees to 60 degrees.

13. A method of fabricating a light emitting diode chip, the method comprising;

forming at least one light emitting structure on a first surface of a substrate; and

forming an alternately laminated bottom structure on an opposing second surface of the substrate, the alternately laminated bottom structure comprising dielectric pairs, each of the dielectric pairs comprising a first material layer comprising a first refractive index and a second material layer comprising a second refractive index, the first refractive index being greater than the second refractive index, the dielectric pairs comprising;

first dielectric pairs comprising the first material layer and the second material layer, the first material layer and the second material layer each having an optical thickness less than λ

/4;

a second dielectric pair comprising the first material layer and the second material layer, one of the first material layer and the second material layer having an optical thickness less than λ

/4 and the other having an optical thickness greater than λ

/4; and

third dielectric pairs comprising the first material layer and the second material layer, each of the first material layer and the second material layer having an optical thickness greater than λ

/4,

wherein λ

is a central wavelength of the visible light range, and

wherein the first dielectric pairs are located closer to or farther from the substrate than the third dielectric pairs.

14. The method of claim 13, wherein forming the alternately laminated bottom structure comprises determining an optical thickness of each layer in the dielectric pairs and a lamination sequence of the dielectric pairs, and sequentially forming the respective layers on the substrate according to the lamination sequence.

15. The method of claim 13, wherein the second dielectric pair is arranged near the center of the alternately laminated bottom structure.

16. The method of claim 13, wherein at least half the first dielectric pairs are located closer to the substrate than a second dielectric pair located closest to the substrate and such that at least half the third dielectric pairs are located farther from the substrate than a second dielectric pair farthest from the substrate.

17. The method of claim 13, wherein at least half the third dielectric pairs are located closer to the substrate than a second dielectric pair located closest to the substrate such that at least half the first dielectric pairs are located farther from the substrate than a second dielectric pair located farthest from the substrate.

18. The method of claim 13, further comprising forming an alternately laminated top structure on the light emitting structure, the alternately laminated top structure configured to transmit light generated in the active layer and to reflect light within at least a partial region of the visible light spectrum, the reflected light has a longer wavelength than light generated in the active region.