Electronic system and method for selectively allowing access to a shared memory

• US 8,314,808 B2
• Filed: 09/21/2011
• Issued: 11/20/2012
• Est. Priority Date: 08/26/1996
• Status: Expired due to Fees

• Current Assignee: Parthenon Unified Memory Architecture LLC (Acacia Research Corporation)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Owen, Jefferson Eugene, Diaz, Raul Zegers, Colavin, Osvaldo
• Primary Examiner(s): NGUYEN, HAU H
• Application Number:
  US13/239,200
• Publication Number:
  US 20120007871A1
• Time in Patent Office: 426 Days
• Field of Search: 345/541, 345/542, 345/531, 345/547, 345/555, 345/535
• US Class Current: 345/541
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/443 OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02

Abstract

An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory based on priority. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Claims

1. An electronic system comprising:

a first device, the first device including;

a first memory interface having a first memory controller;

the first memory interface configured to access a shared memory; and

a first direct memory access (DMA) engine coupled to the first memory interface, the first DMA engine configured to determine a burst length of first data to be communicated through the first memory interface;

a decoder/encoder, the decoder/encoder having;

a second memory interface having a second memory controller, the second memory interface having access to the shared memory; and

a second DMA engine coupled to the second memory interface, the second DMA engine configured to determine a burst length of second data to be communicated through the second memory interface;

an arbiter configured to receive shared memory access requests from the first device and the decoder/encoder, the arbiter configured to arbitrate access to the shared memory; and

a bus configured to pass the first data in real time between the shared memory and the first device and the bus further configured to pass the second data in real time between the shared memory and the decoder/encoder.

2. The electronic system according to claim 1 wherein the first device is a graphics accelerator.

3. The electronic system according to claim 1 wherein the shared memory is a dynamic random access memory (DRAM).

4. The electronic system according to claim 1 wherein the shared memory is a synchronous random access memory (SRAM).

5. The electronic system according to claim 1 wherein the shared memory is monolithically integrated into the electronic system.

6. The electronic system according to claim 1 wherein the decoder/encoder includes a decoder integrated with an encoder into a single integrated circuit.

7. The electronic system according to claim 1 wherein the decoder/encoder includes a decoder and an encoder in separate devices.

8. The electronic system according to claim 1 wherein the decoder/encoder includes a software-based encoder.

9. The electronic system according to claim 1 wherein the arbiter is integrated into the second memory interface.

10. The electronic system according to claim 1 wherein the arbiter dynamically changes priority.

11. The electronic system according to claim 1, comprising:

a third DMA engine coupled to the second memory interface, the third DMA engine configured to determine a burst length of third data to be communicated through the second memory interface, wherein the arbiter is further configured to arbitrate access requests made by a decoder and an encoder.

12. A method comprising:

configuring a first direct memory access (DMA) engine to determine a burst length of first data to be communicated through the a first memory interface to a shared memory over a fast bus, the first DMA engine and the first memory interface configured in a first device;

configuring a second direct memory access (DMA) engine to determine a burst length of second data to be communicated through a second memory interface to the shared memory over the fast bus, the second DMA engine and the second memory interface configured in a decoder/encoder;

receiving a first shared memory access request from the first device;

receiving a second shared memory access request from the decoder/encoder;

arbitrating access to a shared memory, the arbitrating between the first and second shared memory access requests;

passing the first data in real time, via the fast bus, between the shared memory and the first device; and

passing the second data in real time, via the fast bus, between the shared memory and the decoder/encoder.

13. The method according to claim 12 wherein passing the first and second data includes communicating with a dynamic random access memory (DRAM).

14. The method according to claim 12 wherein passing the first and second data includes communicating with a synchronous random access memory (SRAM).

15. The method according to claim 12, comprising:

executing software to encode audio data, the audio data including at least some of the second data.

16. The method according to claim 12, comprising:

executing software to encode video data, the video data including at least some of the second data.

17. The method according to claim 12 wherein arbitrating access to the shared memory includes shifting priority such that a shared memory access request is assigned a first priority when the shared memory access request is received and an increased priority as time passes.

18. The method according to claim 12 wherein arbitrating access to the shared memory includes shifting priority such that two or more shared memory access requests from one device are not consecutively granted when a shared memory access request from another device is pending.

19. The method according to claim 12, comprising:

determining the burst length of the first DMA engine to be between four (4) and seventeen (17) words.