Selective memory cell program and erase

• US 8,315,093 B2
• Filed: 02/15/2012
• Issued: 11/20/2012
• Est. Priority Date: 08/19/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dong, Yingda, Kuo, Tien-chien, Hemink, Gerrit Jan
• Primary Examiner(s): Sofocleous, Alexander
• Assistant Examiner(s): Pham, Hai
• Application Number:
  US13/397,428
• Publication Number:
  US 20120140559A1
• Time in Patent Office: 279 Days
• Field of Search: 365/185.03, 365/185.11, 365/185.18, 365/185.19, 365/185.29
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

Claims

1. A method of operating non-volatile storage comprising single-level blocks and multi-level blocks, the single-level blocks each including a plurality of word lines and a plurality of non-volatile storage elements, the method comprising:

erasing non-volatile storage elements associated with all word lines in a first block of the single-level blocks;

programming data in a first group of the non-volatile storage elements in the first block of the single-level blocks without programming non-volatile storage elements associated with a second group the non-volatile storage elements in the first block of the single-level blocks;

transferring the data from the first group of non-volatile storage elements to one or more of the multi-level cell blocks while the second group of non-volatile storage elements associated remain unprogrammed; and

erasing the data in the non-volatile storage elements associated with at least the first group of non-volatile storage elements.

2. The method of claim 1, wherein the first group of the non-volatile storage elements are associated with even word lines of the plurality word lines, the second group of the non-volatile storage elements are associated with odd word lines of the plurality of word lines.

3. The method of claim 2, further comprising:

programming data in the non-volatile storage elements associated with the odd word lines after erasing the data in the non-volatile storage elements associated with the even word lines;

transferring the data from the non-volatile storage elements associated with the odd word lines to one or more of the multi-level blocks while non-volatile storage elements associated with the even word lines remain erased; and

erasing the data in the non-volatile storage elements associated with the odd word lines.

4. The method of claim 2, wherein the erasing the data in the non-volatile storage elements associated with the even word lines includes erasing only the non-volatile storage elements associated with the even word lines.

5. The method of claim 4, wherein the erasing only the non-volatile storage elements associated with the even word lines includes:

applying one or more erase pulses to the non-volatile storage elements in the first block;

applying a first voltage to the even word lines while applying the one or more erase pulses; and

applying a second voltage to the odd word lines in the first block while applying the one or more erase pulses, the first voltage is lower than the second voltage.

6. The method of claim 1, wherein the programming data in a first group of the non-volatile storage elements in the first block of the single-level blocks without programming non-volatile storage elements associated with a second group the non-volatile storage elements in the first block of the single-level blocks, includes:

programming data in non-volatile storage elements in a checkerboard pattern in the first single-level block without programming approximately half of the non-volatile storage elements in the first single-level block.

7. The method of claim 1, wherein the transferring the data from the first group of non-volatile storage elements to one or more of the multi-level cell blocks while the second group of non-volatile storage elements associated remain unprogrammed includes:

transferring the data from the non-volatile storage elements associated with the checkerboard pattern in the first single-level block to a first multi-level block of the multi-level blocks while the approximately half of the non-volatile storage elements in the first single-level block remain unprogrammed.

8. The method of claim 7, wherein the checkerboard pattern is a first checkerboard pattern and further comprising:

programming data in non-volatile storage elements in a second checkerboard pattern in the first single-level block, non-volatile storage elements that were programmed in the first checkerboard pattern are not programmed using the second checkerboard pattern; and

transferring the data from the non-volatile storage elements associated with the second checkerboard pattern in the first single-level block to a second multi-level block of the multi-level blocks, the transferring occurs while non-volatile storage elements associated with the first checkerboard pattern line remain unprogrammed.

9. The method of claim 8, wherein the second multi-level block and the first multi-level block are the same multi-level block.

10. A non-volatile storage device comprising:

a first set of one or more blocks of non-volatile storage elements;

a second set of one or more blocks of non-volatile storage elements;

a plurality of word lines associated with a first block of the first set of one or more blocks of non-volatile storage elements;

a plurality of bit lines associated with the first block of the first set of one or more blocks of non-volatile storage elements; and

one or more managing circuits in communication with the first set of blocks of non-volatile storage elements and the second set of blocks of non-volatile storage elements, the one or more managing circuits store one bit of data per non-volatile storage element in the first set of blocks, the one or more managing circuits store multiple bits of data per non-volatile storage element in the second set of blocks, the one or more managing circuits erase non-volatile storage elements associated with all word lines in a first block of the first set of blocks, the one or more managing circuits program data in a first group of the non-volatile storage elements in the first block without programming non-volatile storage elements associated with a second group the non-volatile storage elements in the first block, the one or more managing circuits transfer the data from the first group of non-volatile storage elements to one or more blocks of the second set of blocks while the second group of non-volatile storage elements associated remain unprogrammed, the one or more managing circuits erase the data in the non-volatile storage elements associated with at least the first group of non-volatile storage elements.

11. The non-volatile storage device of claim 10, wherein the first group of the non-volatile storage elements are associated with even word lines of the plurality word lines, the second group of the non-volatile storage elements are associated with odd word lines of the plurality of word lines.

12. The non-volatile storage device of claim 11, wherein the one or more managing circuits program data in the non-volatile storage elements associated with the odd word lines after erasing the data in the non-volatile storage elements associated with the even word lines, the one or more managing circuits transfer the data from the non-volatile storage elements associated with the odd word lines to the second group of non-volatile storage elements while non-volatile storage elements associated with the even word lines remain erased, the one or more managing circuits erase the data in the non-volatile storage elements associated with the odd word lines.

13. The non-volatile storage device of claim 11, wherein when the one or more managing circuits erase the data in the non-volatile storage elements associated with the even word lines the one or more managing circuits erase only the non-volatile storage elements associated with the even word lines.

14. The non-volatile storage device of claim 13, wherein when the one or more managing circuits erase only the non-volatile storage elements associated with the even word lines the one or more managing circuits apply one or more erase pulses to the non-volatile storage elements in the first block;

apply a first voltage to the even word lines while applying the one or more erase pulses; and

apply a second voltage to the odd word lines in the first block while applying the one or more erase pulses, the first voltage is lower than the second voltage.

15. The non-volatile storage device of claim 10, wherein when the one or more managing circuits program data in the first group of the non-volatile storage elements in the first block while non-volatile storage elements associated with the second group the non-volatile storage elements in the first block remain unprogrammed, the one or more managing circuits program data in non-volatile storage elements in a checkerboard pattern in the first block, approximately half of the non-volatile storage elements in the first block remain unprogrammed.

16. The non-volatile storage device of claim 15, wherein the one or more managing circuits transfer the data from the non-volatile storage elements associated with the checkerboard pattern in the first block to the one or more blocks of the second set of blocks while the approximately half of the non-volatile storage elements in the first block remain unprogrammed.

17. A method of operating non-volatile storage having a plurality of non-volatile storage elements and a plurality of word lines associated with the plurality of non-volatile storage elements, the method comprising:

erasing data in a first group of non-volatile storage elements;

weakly erasing a second group of the non-volatile storage elements;

programming data in the first group of the non-volatile storage elements while not programming the second group of the non-volatile storage elements, for every non-volatile storage element in the first group any neighbor non-volatile storage element on a word line either above or below the non-volatile storage element in the first group is a member of the second group that is not programmed;

erasing data in the second group of non-volatile storage elements at a time when the second group of non-volatile storage elements are still weakly erased; and

programming the second group of the non-volatile storage elements, for every non-volatile storage element in the second group any neighbor non-volatile storage element on a word line either above or below the non-volatile storage element in the second group is not programmed.

18. The method of claim 17, wherein the erasing data in the second group of non-volatile storage elements at a time when the second group of non-volatile storage elements are still weakly erased includes weakly erasing the first group of the non-volatile storage elements.

19. A method of operating non-volatile storage comprising single-level blocks and multi-level blocks, the single-level blocks each including a plurality of word lines and a plurality of non-volatile storage elements, the method comprising:

performing a normal erase of non-volatile storage elements associated with even word lines in a first block of the single-level blocks while weakly erasing non-volatile storage elements associated with odd word lines in the first block;

programming data in non-volatile storage elements associated with the even word lines of the plurality of word lines, non-volatile storage elements associated with the odd word lines are not programmed; and

transferring the data from the non-volatile storage elements associated with the even word lines to one or more of the multi-level cell blocks, the transferring occurs while non-volatile storage elements associated with the odd word lines remain weakly erased.

20. The method of claim 19, further comprising:

performing a normal erase of non-volatile storage elements associated with the odd word lines in the first block while weakly erasing non-volatile storage elements associated with the even word lines in the first block;

programming data in non-volatile storage elements associated with the odd word lines of the plurality of word lines, non-volatile storage elements associated with the even word lines are not programmed; and

transferring the data from the non-volatile storage elements associated with the odd word lines to one or more of the multi-level cell blocks, the transferring occurs while non-volatile storage elements associated with the even word lines remain weakly erased.