Method and apparatus to implement a reset function in a non-volatile static random access memory

• US 8,315,096 B2
• Filed: 08/24/2011
• Issued: 11/20/2012
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Allan, James D, Ashokkumar, Jayant
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US13/216,546
• Publication Number:
  US 20120213027A1
• Time in Patent Office: 454 Days
• Field of Search: 365/185.08, 365/189.16, 365/154, 365/226
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

The state of a volatile memory cell is set by grounding a power supply to the volatile memory cell and driving a first bit line to the volatile memory cell to a first defined state. The first defined state of the first bit line is controllable independently of a defined state of a second bit line to the volatile memory cell. A word line of the volatile memory cell is driven to a word line state, and the power supply to the volatile memory cell is ungrounded.

Claims

1. A method of setting a state of a volatile memory cell, comprising:

grounding a power supply to the volatile memory cell;

driving a first bit line to the volatile memory cell to a first defined state, the first defined state of the first bit line controllable independently of a defined state of a second bit line to the volatile memory cell;

driving a word line of the volatile memory cell to a word line state; and

ungrounding the power supply to the volatile memory cell.

2. The method of claim 1, further comprising:

the volatile memory cell capable of being coupled and decoupled with a stored state of a nonvolatile counterpart memory cell; and

decoupling the volatile memory cell from the nonvolatile counterpart memory cell during the setting of the state of the volatile memory cell.

3. The method of claim 1, further comprising:

maintaining the first bit line in the first defined state longer than necessary to set a stored state of the volatile memory cell to the first defined state, in order to stress test a first set of transistors of the volatile memory cell.

4. The method of claim 3, further comprising:

driving the first bit line to a second defined state;

independently of the driving the first bit line to the second defined state, driving the second bit line to the first defined state; and

maintaining the first bit line in the second defined state longer than necessary to set a stored state of the volatile memory cell to the second defined state, in order to stress test a second set of transistors of the volatile memory cell.

5. The method of claim 1, further comprising:

the first defined state comprising a higher voltage than a logical HIGH voltage stored by the volatile memory cell during normal operation.

6. The method of claim 5, further comprising:

elevating the temperature of the volatile memory cell above an expected operating temperature while performing the setting of the state of the volatile memory cell.

7. A memory cell, comprising:

a volatile bit storage circuit coupled to first and second bit lines, to a power source, and to a ground node;

a nonvolatile bit storage circuit coupled to receive a stored state of the volatile bit storage circuit;

a reset circuit coupled to the volatile storage circuit, the reset circuit comprising;

a first section coupling the first bit line to a power source that is independent of the power source of the volatile bit storage circuit;

a second section coupling the first bit line to the ground node of the volatile bit storage circuit;

a third section coupling the second bit line to the power source that is independent of the power source of the volatile bit storage circuit;

a fourth section coupling the second bit line to the ground node of the volatile bit storage circuit;

and

a controller configured to control the first and second sections independently of the third and fourth sections.

8. The memory cell of claim 7, further comprising:

the controller configured to control the first section independently of the second section; and

the controller configured to control the third section independently of the fourth section.

9. The memory cell of claim 7, further comprising:

the controller configured to selectively ground the volatile bit storage circuit power source.

10. The memory cell of claim 9, further comprising a current limiting transistor between the volatile bit storage circuit ground node and a ground node of a chip comprising the memory cell.

11. A memory array, comprising:

a plurality of memory cells, each memory cell comprising a volatile bit storage cell and a nonvolatile bit storage cell, each volatile bit storage cell coupled to first and second bit lines and to a volatile bit storage cell power source;

a reset circuit to selectively set all the volatile memory cells of the array each to a same first defined state, the reset circuit comprising;

a reset circuit power source that is independent of the volatile bit storage cell power source;

a first circuit to set a state of the first bit line; and

a second circuit to set a state of the second bit line independently of setting the state of the first bit line.

12. The memory array of claim 11, the reset circuit further comprising a circuit to ground the volatile bit storage cell power source while setting the volatile cells to the first defined state.

13. The memory array of claim 12, the circuit to ground the volatile bit storage cell power source further comprising current limiting transistors coupled between the ground node of each volatile bit storage cell and a ground node for the memory array.

14. The memory array of claim 11, the reset circuit further comprising a circuit to ground the first and second bit lines to the ground node of the volatile bit storage cell independently of one another.

15. The memory array of claim 11, the reset circuit further comprising a circuit to charge the first and second bit lines independently of one another via the reset circuit power source.

16. A method of setting a plurality of volatile memory cells of a memory array to a same defined state, the method comprising:

grounding a power supply to the volatile memory cells;

driving first bit lines to the volatile memory cells to a first defined state, the first defined state of the first bit lines controllable independently of a state of a second bit line to the volatile memory cells;

setting a state of word lines to the volatile memory cells;

ungrounding the power supply to the volatile memory cells.

17. The method of claim 16, further comprising:

each volatile memory cell capable of being coupled and decoupled from a stored state of a nonvolatile counterpart memory cell; and

maintaining each volatile memory cell in a decoupled state from the nonvolatile counterpart memory cell while setting the state of the volatile memory cells.

18. The method of claim 16, further comprising:

maintaining the first bit lines in the first defined state longer than necessary to set the state of the volatile memory cells to the first defined state, in order to stress test a first set of transistors of each volatile memory cell.

19. The method of claim 18, further comprising:

driving the first bit lines to a second define state different than the first defined state;

independently of the driving of the first bit lines to the second defined state, driving the second bit lines to the first defined state; and

maintaining the first bit lines in the second defined state longer than necessary to set the volatile memory cells to the second defined state, in order to stress test a second set of transistors of each volatile memory cell.

20. The method of claim 16, further comprising:

the first defined state comprising a higher voltage than a logical HIGH bit value stored by the volatile memory cells during normal operation.