System and method for biasing CMUT elements

• US 8,315,125 B2
• Filed: 03/18/2010
• Issued: 11/20/2012
• Est. Priority Date: 03/18/2009
• Status: Active Grant

• Current Assignee: Sonetics Ultrasound, Inc.
• Original Assignee: Sonetics Ultrasound, Inc.
• Inventors: Lemmerhirt, David F.
• Primary Examiner(s): COLON SANTANA, EDUARDO
• Application Number:
  US12/727,143
• Publication Number:
  US 20100237807A1
• Time in Patent Office: 978 Days
• Field of Search: 367 93- 94, 367/138, 367/140, 318/116, 295/94, 310/300, 601/2
• US Class Current: 367/140
• CPC Class Codes: G01H 11/06 by electric means
• CPC Class Codes: G01S 7/52017 particularly adapted to short-range imaging G01S7/53 takes precedence
• CPC Class Codes: Y10T 29/49005 Acoustic transducer

Abstract

A system and method for biasing a capacitive ultrasonic transducer (CMUT) device with a circuit that includes a CMUT that includes a first plate and a second plate that form a membrane structure; a circuit voltage source at a complementary metal-oxide-semiconductor (CMOS) compatible voltage; a bias voltage source that applies a bias voltage greater than a CMOS compatible voltage and is applied to the first plate; and readout electronics with an input connected on the second plate side of the circuit.

Claims

1. A system for biasing a capacitive ultrasonic transducer (CMUT) device comprising:

a circuit including

a CMUT that includes a first plate and a second plate that form a membrane structure;

a bias voltage source that applies a bias voltage greater than a complementary metal-oxide-semiconductor (CMOS) compatible voltage and is applied to the first plate; and

readout electronics with an input connected on the second plate side of the circuit; and

a circuit voltage source that applies a CMOS compatible voltage to the readout electronics.

2. The system of claim 1, further comprising a bias impedance element between the circuit voltage source and the second plate.

3. The system of claim 2, wherein the bias impedance element is a resistor.

4. The system of claim 1, further comprising a direct current (DC) blocking capacitor between the bias voltage and the readout electronics.

5. The system of claim 4, wherein the CMUT acts as the DC blocking capacitor.

6. The system of claim 5, wherein the circuit is a CMOS circuit with a dielectric layer, wherein the first plate is on the dielectric layer.

7. The system of claim 4, further comprising a pulse signal voltage source that applies a transmit signal to the CMUT when in a transmit mode, and a transmit/receive (T/R) switch that toggles according to the transmit mode and a receive mode of the CMUT.

8. The system of claim 7, wherein the T/R switch selectively connects the input of the readout electronics and second plate of the CMUT to the circuit voltage source during transmit mode.

9. The system of claim 8, wherein the T/R switch has an impedance that in combination with a complex impedance of the CMUT creates a voltage divider during the transmit mode.

10. The system of claim 7, wherein the pulse voltage source has a voltage range greater than 15 volts.

11. The system of claim 7, wherein the readout electronics includes a protection diode before the input of the readout electronics.

12. The system of claim 4, wherein the bias voltage source applies a voltage magnitude greater than a CMOS compatible voltage.

13. The system of claim 12, wherein the bias voltage alternates polarity according to events related to receiving or transmission of a signal.

14. The system of claim 12, wherein the bias voltage alternates polarity at a frequency less than 100 kHz.

15. A method for biasing a capacitive ultrasonic transducer (CMUT) device with a first plate and a second plate comprising:

reading measurements from a connection on the second plate side of the CMUT, wherein the measurements are made with complementary metal-oxide-semiconductor (CMOS) components;

biasing the first plate of the CMUT with a voltage source that has a voltage magnitude greater than a CMOS compatible voltage; and

blocking the biasing voltage source from the CMOS compatible components.

16. The method of claim 15, wherein blocking the biasing voltage includes the CMUT acting as a blocking capacitor.

17. The method of claim 15, further comprising applying a pulse voltage signal to the first plate of the CMUT wherein the voltage range of the pulse voltage signal is greater than the CMOS compatible voltage and includes connecting a node on the second plate side of the CMOS circuit to a CMOS compatible voltage by toggling a switch.

18. The method of claim 15, wherein the biasing voltage source is a direct current (DC) voltage source.

19. The method of claim 15, further comprising alternating the polarity of the biasing voltage source.