Single transducer full duplex talking circuit

• US 8,315,379 B2
• Filed: 03/24/2008
• Issued: 11/20/2012
• Est. Priority Date: 11/10/2004
• Status: Active Grant

• Current Assignee: Soundec Co., Ltd.
• Original Assignee: Matech Inc .
• Inventors: Masuda, Masahisa, Kitazumi, Gontaro
• Primary Examiner(s): Jamal, Alexander
• Application Number:
  US12/054,320
• Publication Number:
  US 20080170515A1
• Time in Patent Office: 1,702 Days
• Field of Search: 379/406.08, 381/163
• US Class Current: 379/406.08
• CPC Class Codes: H04B 3/20 Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other
• CPC Class Codes: H04M 9/082 using echo cancellers echo cancellers per se H04B3/23

Abstract

A full duplex talking audio circuit uses a single transducer Z_T which, even when various characteristics including the strength of a transmission signal change from moment to moment, enables the adequate operation of an echo canceling function and sufficiently compensates for the deterioration of the frequency characteristics of the transmission signal due to the acoustic transfer characteristics of the human body.

Claims

1. A single-transducer full duplex circuit, comprising:

connecting terminals for connecting to an external digital circuit including an input terminal (D_IN) into which a digital reception input signal is input, an output terminal (D_OUT) into which a digital transmission output signal is output, and a learning activation input terminal (I_LN);

an analog signal processing circuit including;

an analog differential output amplifier (A_DO) which amplifies the output from a D/A converter (DAC);

a bridge circuit consisting of first, second, and third resistors (R1, R2, and R3) and a single transducer (Z_T) which are driven by an output of said analog differential output amplifier (A_DO); and

an analog differential input amplifier (A_DI) which amplifies an equilibrium signal output by said bridge circuit, wherein an analog output signal of said analog differential input amplifier (A_DI) is supplied to an A/D converter (ADC);

a digital signal processing circuit including;

a signal generator (SG);

a first high pass filter (HPF1) into which said digital reception input signal is input through said input terminal (D_IN);

a first multiplier (MUL1) which multiplies an output of said high pass filter (HPF1) by a reception volume coefficient (R_RXV);

a second multiplier (MUL2) which multiplies an input from said signal generator (SG) by a signal volume coefficient register (R_SGV);

an adder (ADD) which adds an output of said first multiplier (MUL1) and an output of said second multiplier (MUL2), wherein an output of said adder (ADD) is supplied to said D/A converter (DAC) which converts it into an analog signal;

a first signal delayer and power calculator (DL1) which delays the output of said adder (ADD) and calculates a first moving average power value (PW1);

a second signal delayer and power calculator (DL2) which delays an output of said first signal delayer and power calculator (DL1) and calculates a second moving average power value (PW2);

a delayed signal memory (X_A[k]) which sequentially stores an output of said second signal delayer and power calculator (DL2);

a transfer function identification filter (FIL_ID) into which the output of said delayed signal memory (X_A[k]) is input;

a first filter coefficient memory (H_A[k]) which stores a filter coefficient corresponding to said transfer function identification filter (FIL_ID);

a second high pass filter (HPF2) into which an output of said A/D converter (ADC) is input;

a fourth signal delayer (DL4) into which an output of said second high pass filter (HPF2) is input;

a subtracter (SUB) which subtracts an output of said transfer function identification filter (FIL_ID) from an output of said fourth signal delayer (DL4);

a fourth multiplier (MUL4) which multiplies an output of said subtracter (SUB) by a transmission volume coefficient (R_TXV);

a third signal delayer and power calculator (DL3) which delays an output of said fourth multiplier (MUL4) and calculates a third moving average power value (PW3);

an equalization filter (FIL_EQ) into which an output of said third signal delayer and power calculator (DL3) is input; and

a second filter coefficient memory which stores a filter coefficient (H_EQ[k]) of said equalization filter (FIL_EQ),

wherein the transmission output terminal (D_OUT) is driven by the digital transmission output signal output from said equalization filter (FIL_EQ) and the first filter coefficient (H_A[k]) corresponding to said transfer function identification filter FIL_ID identifies the transfer function from an input end of said D/A converter (DAC) to a output end of said second high pass filter (HPF2) via said analog signal processing circuit.

2. The single-transducer full duplex circuit according to claim 1 wherein:

said bridge circuit in said analog signal processing circuit is set to an equilibrium condition using the output of said analog differential output amplifier (A_DO) which drives said transducer (Z_T) when said transducer (Z_T) is in operation;

said third resistor (R3) being configured with a fixed resistance, variable resistance, or electronically variable resistance in order to satisfy the equilibrium condition; and

the output of the D/A converter (DAC) is divided by resistance from a differential output of said differential output amplifier (A_DO) and converted from an electrical signal to an acoustic signal by said transducer (Z_T).

3. The single-transducer full duplex circuit according to claim 1 wherein:

a first voltage is obtained by dividing the output of said differential output amplifier (A_DO) with said first resistor (R1) and said second resistor (R2), the first voltage is used as a first input for said differential input amplifier (A_DI);

a second voltage is obtained by dividing the output of said differential output amplifier with said third resistor (R3) and said transducer (Z_T);

a third voltage is obtained by summing the second voltage with a voltage converted to electromotive force from transmission acoustic vibration by said transducer (Z_T), the third voltage is used as a second input for said differential input amplifier (A_DI); and

a differential signal of the voltages on the first and second inputs is amplified by said differential input amplifier (A_DI).

4. The single-transducer full duplex circuit according to claim 1, characterized in that said digital signal processing circuit has a function in which the first filter coefficient (H_A[k]) corresponding to said transfer function identification filter (FIL_ID) is dynamically corrected in accordance with changes in acoustic impedance when said transducer (Z_T) is in operation.

5. The single-transducer full duplex circuit according to claim 1 wherein the second filter coefficient (H_EQ[k]) corresponding to said equalization filter (FIL_EQ) stored in said second filter coefficient memory is a tap coefficient which corrects acoustic inconsistencies in electrical signals generated by said transducer (Z_T) due to transmission acoustic vibration, the second filter coefficient (H_EQ[k]) adjusting the digital transmission output signal to have acoustic characteristics similar to the acoustic vibration generated from an actual sound source.

6. The single-transducer full duplex talking circuit according to claim 1 wherein said digital signal processing circuit further comprises;

a correction intensity coefficient register (R_mu) which holds a correction coefficient (mu);

a third multiplier (MUL3) which multiplies said correction coefficient (mu) by an error signal (err), the error signal being the output of said subtracter (SUB),

wherein a coefficient updating algorithm (AL_UPD) repeatedly computes the first filter coefficient (H_A[k]) corresponding to said transfer function identification filter (FIL_ID) based on the output of said third multiplier (MUL3), and said coefficient updating algorithm (AL_UPD) supplies the first filter coefficient (H_A[k]) to said transfer function identification filter (FIL_ID) and updates said first filter coefficient (H_A[k]) as a result of convergence of the computations for the first filter coefficient (H_A[k]).

7. The single-transducer full duplex circuit according to claim 6 wherein a system identification correction intensity calculation algorithm (AL_mu) in said digital signal processing circuit dynamically controls the convergence time and convergence error of the repeated computation of said filter coefficient (H_A[k]) of said transfer function identification filter (FIL_ID) according to said first moving average power value (PW1).

8. The single-transducer full duplex circuit according to claim 6 wherein an erroneous correction detection and simultaneous talking detection algorithm (AL_DBL) in said digital signal processing circuit updates said first filter coefficient (H_A[k]) and assesses whether to dynamically update the first filter coefficient (H_A[k]) by comparing said second moving average power value (PW2) with said third moving average power value (PW3).

9. The single-transducer full duplex talking circuit according to claim 6 wherein a transfer function identification filter learning algorithm (AL_LN) in said digital signal processing circuit is forcibly activated when said error signal (err) exceeds a certain value, whereupon AL_LN generates a standard signal using the signal generator (SG), updates the coefficient updating algorithm (AL_UPD), and recalculates the first filter coefficient (H_A[k]) corresponding to said transfer function identification filter (FIL_ID).

10. An audio circuit, comprising:

an analog circuit including a differential output amplifier, a differential input amplifier, and a bridge circuit coupled between the differential output amplifier and the differential input amplifier; and

a digital signal processing circuit configured to generate a first set of filter coefficients (H_A[k]) from a first signal input into the analog circuit and generate a second set of filter coefficients from a second signal output from the analog circuit, the digital signal processing circuit generating a transfer function identification filter (FIL_ID) from the first and second set of filter coefficients and generating an output signal from the transfer function identification filter (FIL_ID) that is applied to the second signal output from the analog circuit, wherein a transfer function identification filter learning algorithm (AL_LN) in said digital signal processing circuit is activated in response to an error signal (err) exceeding a certain value, whereupon AL_LN initiates generation of a standard signal using a signal generator (SG), updates a coefficient updating algorithm (AL_UPD), and recalculates the first set filter coefficient (H_A[k]) for the transfer function identification filter (FIL_ID).

11. The audio circuit according to claim 10 further comprising:

an D/A converter DAC coupling the first signal input to the differential output amplifier via a first high pass filter; and

a A/D converter (ADC) coupling the second signal output from the analog circuit to a second high pass filter in the digital signal processing circuit.

12. The audio circuit according to claim 11 wherein the second set of filter coefficients are associated with a transfer function filter for a signal pathway from the DAC, through the analog circuit and ADC, and to the second high pass filter.

13. The audio circuit according to claim 10 wherein the digital signal processing circuit further comprises:

a first signal delayer and power calculator (DL1) configured to delay the first signal input and calculate a first moving average power value (PW1);

a second signal delayer and power calculator (DL2) configured to delay an output of said first signal delayer and power calculator (DL1) and calculate a second moving average power value (PW2);

a delayed signal memory (X_A[k]) configured to sequentially store an output of the second signal delayer and power calculator (DL2), wherein the transfer function identification filter (FIL_ID) is configured to receive an output of the delayed signal memory (X_A[k]);

a fourth signal delayer (DL4) configured to receive an output signal from the analog circuit;

a subtracter SUB configured to subtract an output of the transfer function identification filter (FIL_ID) from an output of said fourth signal delayer (DL4);

a fourth multiplier (MUL4) configured to multiply an output of the subtracter (SUB) by a transmission volume coefficient (R_TXV);

a third signal delayer and power calculator (DL3) configured to delay an output of the fourth multiplier (MUL4) and calculate a third moving average power value (PW3);

an equalization filter (FIL_EQ) configured to receive an output of the third signal delayer and power calculator (DL3).

14. An apparatus, comprising:

an analog signal processing circuit comprising a transducer (Z_T); and

a digital signal processing circuit comprising;

a first input configured to receive a reception signal;

a first output configured to output a transmission signal;

a second output coupled to an input of the analog signal processing circuit;

a second input coupled to an output of the analog signal processing circuit;

a transfer function identification filter (FIL_ID) configured to identify a transfer function of the analog signal processing circuit, wherein the digital signal processing circuit is further configured to dynamically correct filter coefficients (H_A[k]) for the transfer function identification filter (FIL_ID) according to changes in acoustic impedance of the transducer (Z_T);

a system identification correction intensity calculation algorithm (AL_mu) configured to dynamically control a convergence time and a convergence error of the filter coefficients (H_A[k]) for the transfer function identification filter (FIL_ID) according to a first moving average power value (PW1) of the reception signal, and

an erroneous correction detection and simultaneous talking detection algorithm (AL_DBL) configured to update the filter coefficients (H_A[k]) and assess whether to dynamically update the filter coefficients (H_A[k]) by comparing a second moving average power value (PW2) of the reception signal with a third moving average power value (PW3) of the transmission signal.

15. The apparatus according to claim 14 wherein the digital signal processing circuit further comprises a transfer function identification filter learning algorithm (AL_LN) configured to forcibly activate when an error signal (err) exceeds a certain value and generate a standard signal using a signal generator (SG), update a coefficient updating algorithm (AL_UPD), and recalculate the filter coefficients (H_A[k]) corresponding to the transfer function identification filter (FIL_ID).

16. The apparatus according to claim 14 wherein the digital signal processing circuit is configured to dynamically control a convergence time and convergence error of the filter coefficient (H_A[k]) according to the first moving average power value (PW1) of the reception signal.

17. The apparatus according to claim 16 wherein the digital signal processing circuit is further configured to dynamically control the convergence time and convergence error of the filter coefficient (H_A[k]) by varying an amplitude level of a control signal and combining the control signal with the reception signal.

18. The apparatus according to claim 14 wherein the digital signal processing is further configured to assess whether to dynamically update the filter coefficient (H_A[k]) according to a signal strength of the reception signal and a signal strength of the transmission signal.

19. The apparatus according to claim 18 wherein the digital signal processing is further configured to stop updating the filter coefficient (H_A[k]) when the signal strength of the transmission signal and the reception signal indicate a simultaneous talking state.

20. The apparatus according to claim 14 wherein the analog signal processing circuit comprises:

an analog differential output amplifier (A_DO) coupled through a D/A converter (DAC) to the second output of the digital signal processing circuit;

an analog differential input amplifier (A_DI) coupled through an A/D converter (ADC) to the second input of the digital signal processing circuit; and

a bridge circuit consisting of first, second, and third resistors (R1, R2, and R3) and the transducer (Z_T), the bridge circuit coupled between the analog differential output amplifier (A_DO) and the analog differential input amplifier (A_DI).