Cache memory including a predict buffer

• US 8,316,187 B2
• Filed: 07/08/2008
• Issued: 11/20/2012
• Est. Priority Date: 07/08/2008
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pothireddy, Anil
• Primary Examiner(s): Campos, Yaima
• Assistant Examiner(s): VO, THANH DUC
• Application Number:
  US12/169,091
• Publication Number:
  US 20100011169A1
• Time in Patent Office: 1,596 Days
• Field of Search: None
• US Class Current: 711/137
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache

Abstract

Disclosed is a cache memory, design structure, and corresponding method for improving cache performance comprising one or more cache lines of equal size, each cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and a predict buffer, of size equal to the size of the cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous access request.

Claims

1. A cache memory comprising:

one or more cache lines of equal size, each said cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and

a predict buffer, of size equal to the size of said cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous said access request to the same cache block in said cache memory, wherein said next block of data from said main memory having an address next to an address of said same cache block in said memory;

wherein said predict-fetch signal is generated by comparing a number of successive cache hits generated by said access requests from said processor to said same cache block with a predetermined threshold and asserting said predict-fetch signal based on said comparison, wherein said generating further comprises comparing, if an access request by said processor generates a cache miss, an address of a requested cache block with an address of the cache block in said predict buffer and moving the cache block in the predict buffer to one of said cache lines based on said comparison, wherein if a predict-fetch from the main memory is in progress, the number of the successive cache hits is reset.

2. The cache memory of claim 1, wherein said predict-fetch signal is not asserted if said next cache block is already stored in a cache line of said cache memory.

3. The cache memory of claim 1, wherein said predict-fetch signal is not asserted if said next cache block is already stored in said predict buffer.

4. The cache memory of claim 1, wherein said data from said main memory comprises instructions for said processor.

5. A method of storing a block of data in a cache memory, said method comprising:

comparing a number of successive cache hits generated by access requests from a processor to the same cache block already stored within said cache memory with a predetermined threshold, and

storing, based on said comparison, a next block of data from a main memory in said cache memory, said next block having an address next to the address of said same cache block in said main memory, wherein said next block of data is stored in a predict buffer in said cache memory, wherein the cache memory comprises one or more cache lines, and wherein said predict buffer is of size equal to a size of each of the cache lines in said cache memory, wherein if a predict-fetch from the main memory is in progress, the number of successive cache hits is reset; and

comparing, if an access request by said processor generates a cache miss, an address of a requested cache block with an address of the cache block in said predict buffer and moving the cache block in the predict buffer to one of said cache lines based on said comparison.

6. The method of claim 5, wherein said next block of data is not stored if said next cache block is already stored in a cache line of said cache memory.

7. The method of claim 5, wherein said data from said main memory comprises instructions for said processor.

8. A design structure embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

one or more cache lines of equal size, each said cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and

a predict buffer, of size equal to the size of said cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous said access request to the same cache block in one of said cache lines, wherein said next block of data from said main memory has an address next to an address of said same cache block in said main memory, wherein said predict-fetch signal is generated by comparing a number of successive cache hits generated by said access requests from said processor to said same cache block with a predetermined threshold and asserting said predict-fetch signal based on said comparison, wherein said generating further comprises comparing, if an access request by said processor generates a cache miss, an address of a requested cache block with an address of the cache block in said predict buffer and moving the cache block in the predict buffer to one of said cache lines based on said comparison, wherein if a predict-fetch from the main memory is in progress, the number of successive cache hits is reset.