Computer architecture and method of operation for multi-computer distributed processing having redundant array of independent systems with replicated memory and code striping

• US 8,316,190 B2
• Filed: 03/19/2008
• Issued: 11/20/2012
• Est. Priority Date: 04/06/2007
• Status: Active Grant

• Current Assignee: Waratek Limited (Waratek Holdings Ltd.)
• Original Assignee: Waratek Pty Limited
• Inventors: Holt, John M.
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): Faal, Baboucarr
• Application Number:
  US12/051,701
• Publication Number:
  US 20080250213A1
• Time in Patent Office: 1,707 Days
• Field of Search: None
• US Class Current: 711/148
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/2028 eliminating a faulty processor or activating a spare
• CPC Class Codes: G06F 11/203 using migration
• CPC Class Codes: G06F 11/2035 without idle spare hardware
• CPC Class Codes: G06F 9/526 Mutual exclusion algorithms
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues

Abstract

Computers and other computing machines and information appliances having a modified computer architecture and program structure which enables the operation of an application program concurrently or simultaneously on a plurality of computers interconnected via a communications link or network using a special distributed runtime (DRT), and that provides for a redundant array of independent computing systems that include computer code distribution using code-striping onto the plurality of the computers or computing machines. A redundant array of independent computing systems operating in concert and code-striping features.

Claims

1. A method for striping computer program code across a plurality of computing machines in a multiple computer system including the plurality of computing machines, each computing machine having a processor and each processor having an associated local memory that is only accessible by an associated processor from among the plurality of processors, the method comprising:

replicating at least a portion of stored memory data contents from each local memory into the local memory of each of the plurality of computing machines;

interconnecting the plurality of computing machines by a communications network;

updating, via said communications network, a replicated memory content value in each other of the plurality of local memory every time a replicated local memory location is written to in any one or the local memory of the plurality of computing machines so that replicated memory locations remain substantially consistent between all of the computing machines, the updating including transmitting, via said communications network, the updated content value from the computing machine that performed the content value update to other ones of the plurality of computing machines and receiving of the updated content value by the other ones of the plurality of computing machines;

satisfying all computing machine memory access requirements from the processor, including read access and write access, substantially exclusively by access to the associated local memory for memory content that is part of the replicated memory, and preventing access to memory that is resident in a different one of the plurality of computing machines; and

replicating at least a portion of an executable code of an application program, the executable code of the application program being different from the replicated memory data contents that result from the execution of the application program code, on each of the plurality of computing machines, where replication is configured for variations of the executable code so that different computing machine operational requirements may be realized, and permits but does not require an exact copy of the executable code on each of the plurality of computing machines.

2. A method as in claim 1, wherein the code-striping comprises an arrangement of in-memory computer program executable code replicated on the plurality of computing machines.

3. A method as in claim 1, wherein the code-striping further comprises procedures for updating and manipulating the in-memory data.

4. A method as in claim 1, wherein the code-striping comprises an arrangement of in-memory computer program executable code replicated on the plurality of computing machines, and procedures for updating and manipulating the in-memory data.

5. A method as in claim 1, the method further comprising:

a contention controller that allows the plurality of computing machines to update corresponding replicated memory locations concurrently and resolve any conflicts or inconsistencies arising with such updating.

6. A method as in claim 5, wherein the contention controller comprises at least one of:

a contention detector,

a contention detector and contention resolver,

a contention detector with messenger and a modified message format,

a contention detector with data consolidation, and

a contention resolver with echo cancellation, and any combination of two or more of these.

7. A method as in claim 1, further comprising synchronizing updating of replicated memory locations between and among the plurality of computing machines.