Method and apparatus for fail-safe start-up circuit for subthreshold current sources

• US 8,316,245 B1
• Filed: 12/11/2008
• Issued: 11/20/2012
• Est. Priority Date: 12/11/2008
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Isik, Tacettin
• Primary Examiner(s): Elamin, M
• Application Number:
  US12/333,149
• Time in Patent Office: 1,440 Days
• Field of Search: 713/30, 713/330, 713/340, 327/142, 327/143, 327/198
• US Class Current: 713/300
• CPC Class Codes: H03L 3/00 Starting of generators

Abstract

A method and apparatus for fail-safe start-up circuit for subthreshold current sources have been disclosed.

Claims

1. An apparatus comprising counting means for controlling current to a current source during power up, wherein said counting means is operatively coupled to fully discharge a charge storage device when said current source is powered up.

2. The apparatus of claim 1 further comprising an oscillator operatively coupled to said counting means.

3. The apparatus of claim 2 further comprising a first comparison circuit having one or more inputs and an output, said first comparison circuit one or more inputs operatively coupled to said counting means and said first comparison circuit output operatively coupled to reset said counting means.

4. The apparatus of claim 3 further comprising a second comparison circuit having one or more inputs and an output, said second comparison circuit one or more inputs operatively coupled to said counting means and said second comparison circuit output operatively coupled to control said current to said current source.

5. The apparatus of claim 4 wherein said charge storage device is a capacitor, said means for controlling current is a transistor means, said counting means is a ripple counter means, said first comparison circuit is a logic circuit, and said second comparison circuit is a logic circuit.

6. A method comprising:

increasing current to a current source during a power-up;

counting pulses from an oscillator during said power-up;

determining when said counted pulses reach a criteria; and

decreasing current to said current source when said criteria is reached, wherein said criteria is substantially an equal number of positive and negative pulses.

7. The method of claim 6 wherein said criteria is pre-specified count.

8. The method of claim 6 wherein said decreasing current comprises turning off a transistor.

9. A method comprising:

increasing current to a current source during a power-up;

counting pulses from an oscillator during said power-up;

determining when said counted pulses reach a criteria;

decreasing current to said current source when said criteria is reached;

charging a capacitor coupled to an oscillator during said power-up; and

discharging said capacitor when said criteria is reached.

10. An apparatus comprising:

a first switch operatively coupled shunting an existing current flow;

a delay element having an input and an output, said delay element input operatively coupled to a charging circuit;

a counter having an input and an output, said counter input operatively coupled to said delay element output;

a logic circuit having an input and an output, said logic circuit input operatively coupled to said counter output; and

said logic circuit output operatively coupled to said first switch.

11. The apparatus of claim 10 further comprising:

a second switch operatively coupled shunting a charging element in said charging circuit; and

said logic circuit output operative coupled to said second switch.

12. The apparatus of claim 10 wherein said logic circuit input further comprises a plurality of inputs, said plurality of logic circuit inputs operatively coupled to one or more outputs from said counter.

13. The apparatus of claim 12 further comprising a second logic circuit having an input and an output, said second logic circuit input operatively coupled to said counter output and

said second logic circuit output operatively coupled to said counter.

14. The apparatus of claim 12 wherein said second logic circuit input further comprises a plurality of inputs, said plurality of second logic circuit inputs operatively coupled to one or more outputs from said counter.