Error correcting device, method of error correction thereof, and memory device and data processing system including of the same

• US 8,316,280 B2
• Filed: 03/10/2010
• Issued: 11/20/2012
• Est. Priority Date: 03/18/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chang, Sil Wan, Yu, Bum Seok, Jeong, Sang Kyoo, Lee, Dong Gi
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US12/720,903
• Publication Number:
  US 20100241930A1
• Time in Patent Office: 986 Days
• Field of Search: None
• US Class Current: 714/769
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/13 Linear codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2927 Decoding strategies
• CPC Class Codes: H03M 13/37 Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
• CPC Class Codes: H03M 13/3776 using a re-encoding step during the decoding process

Abstract

An error correction device is provided. The error correction device includes a code storage unit where a plurality of error correction codes are stored, a first error correction unit to correct a data error detected from input data by using one of a plurality of error correction codes and to output correction data, a buffer to store the correction data, and a second error correction unit to generate a new correction code from the correction data, to compare another of a plurality of error correction codes with the new correction code and to output a comparison result.

Claims

1. An error correction device comprising:

a code storage unit to store a plurality of error correction codes;

a first error correction unit to correct a data error detected from input data by using one of the plurality of error correction codes and to output correction data;

a buffer to store the correction data; and

a second error correction unit to generate a new correction code from the correction data, to compare another of the plurality of error correction codes with the new correction code and to output a comparison result,

wherein the buffer outputs the correction data to update the input data according to the comparison result output from the second error correction unit.

2. The error correction device of claim 1, wherein the plurality of error correction codes comprises:

a first correction code and a second correction code,

wherein the first error correction unit includes;

a correction unit to detect the data error from the input data, to correct the data error by using the first correction code, and to output the correction data; and

a correction information storage unit to store correction information of the input data.

3. The error correction device of claim 2, wherein the code storage unit updates the first correction code according to the correction information.

4. The error correction device of claim 1, wherein the plurality of error correction codes comprise:

a first correction code and a second correction code,

wherein the second error correction unit includes;

a correction code generation unit to generate the new correction code from the correction data;

a comparison unit to compare the second correction code with the new correction code and to output the comparison result; and

a comparison result storage unit to store the comparison result.

5. The error correction device of claim 1, wherein the plurality of error correction codes are error correction codes (ECC) or cyclic redundancy check (CRC) codes.

6. The error correction device of claim 1, wherein the error correction device further comprises a direct memory access (DMA) controller to control an operation of the error correction device according to an input control signal.

7. A memory device comprising:

a memory to store input data; and

an error correction device to correct a data error detected from the input data, including;

a code storage unit to store a plurality of error correction codes;

a first error correction unit to correct a data error detected from the input data by using one of the plurality of error correction codes and to output correction data;

a buffer to store the correction data; and

a second error correction unit to generate a new correction code from the correction data, to compare another of the plurality of error correction codes with the new correction code and to output a comparison result,

wherein the buffer outputs the correction data to update the input data according to the comparison result output from the second error correction unit.

8. The memory device of claim 7, wherein the memory device is a dynamic random access memory (DRAM) or a static random access memory (SRAM).

9. The memory device of claim 7, wherein the error correction device operates during idle time of the memory device.

10. The memory device of claim 7, wherein the plurality of error correction codes comprises:

a first correction code and a second correction code,

wherein the first error correction unit includes;

a correction unit to detect the data error from the input data, to correct the data error by using the first correction code and to output the correction data; and

a correction information storage unit to store correction information of the input data.

11. The memory device of claim 10, wherein the code storage unit updates the first correction code according to the correction information.

12. The memory device of claim 7, wherein the plurality of error correction codes comprise:

a first correction code and a second correction code,

wherein the second error correction unit includes;

a correction code generation unit to generate the new correction code from the correction data;

a comparison unit to compare the second correction code with the new correction code and to output the comparison result; and

a comparison result storage unit to store the comparison result.

13. A data processing system comprising:

a host; and

a data processing device to communicate with the host,

wherein the data processing device comprises;

a first memory to correct a data error that is detected from input data input from the host, and to output corrected data; and

a second memory to receive and store the corrected data from the first memory,

wherein the first memory comprises;

a memory where the input data is stored; and

an error correction device to correct a data error detected from the input data, including;

a code storage unit to store a plurality of error correction codes;

a first error correction unit to correct a data error detected from the input data by using one of the plurality of error correction codes and to output correction data;

a buffer to store the correction data; and

a second error correction unit to generate a new correction code from the correction data, to compare another of the plurality of error correction codes with the new correction code and to output a comparison result,

wherein the buffer outputs the correction data to update the input data according to the comparison result output from the second error correction unit.

14. The system of claim 13, wherein the data processing device is a solid state drive (SSD).

15. The system of claim 13, wherein the plurality of error correction codes comprises:

a first correction code and a second correction code,

wherein the first error correction unit includes;

a correction unit to detect the data error from the input data, to correct the data error by using the first correction code and to output the correction data; and

a correction information storage unit to store correction information of the input data.

16. The system of claim 15, wherein the code storage unit updates the first correction code according to the correction information.

17. The system of claim 13, wherein the plurality of error correction codes comprises:

a first correction code and a second correction code,

wherein the second error correction unit includes;

a correction code generation unit to generate the new correction code from the correction data;

a comparison unit to compare the second correction code with the new correction code and outputting the comparison result; and

a comparison result storage unit to store the comparison result.