Integrated circuit package and method of making the same

• US 8,318,287 B1
• Filed: 01/19/2011
• Issued: 11/27/2012
• Est. Priority Date: 06/24/1998
• Status: Expired due to Fees

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Glenn, Thomas P.
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): PATHAK, SHANTANU
• Application Number:
  US13/009,690
• Time in Patent Office: 678 Days
• Field of Search: None
• US Class Current: 428/123
• CPC Class Codes: H01L 21/4842 Mechanical treatment, e.g. punching, cutting, deforming, cold welding
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49503 characterised by the die pad
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01037 Rubidium [Rb]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49146 : with encapsulating, e.g., potting, etc.
• CPC Class Codes: Y10T 29/49155 : Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49171 : with encapsulating
• CPC Class Codes: Y10T 428/24207 : with strand[s] or strand-portion[s] between layers [e.g., upholstery trim, etc.]

Abstract

Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Claims

1. An integrated circuit chip package, comprising:

a die pad defining opposed first and second die pad surfaces, and a die pad side surface extending to at least the first die pad surface;

at least one connector integrally connected to the die pad;

a plurality of leads, wherein all of the leads in the integrated circuit chip package are electrically isolated from the die pad and the connector, each of the leads defining opposed first and second lead surfaces, first and second lead side surfaces which each extend to at least the first lead surface, a first end portion defining a first end surface which extends to at least the first lead surface, and a second end portion defining a second end surface which extends between the first and second lead surfaces;

at least one reentrant portion extending fully around the die pad side surface and through the connector;

at least one reentrant portion extending within at least portions of the first end surface and the first and second lead side surfaces of each of the leads, the reentrant portions of the die pad and the leads being used for enhancing the connection between the die pad, the leads, and an encapsulant material applied to the die pad and the leads; and

an integrated circuit die attached to the first die pad surface of the die pad and electrically connected to the first lead surfaces of at least some of the leads;

the encapsulant material being applied to at least portions of the integrated circuit die, the connector, the first die pad surface and the die pad side surface of the die pad, and the, first lead surface, the first end surface, and the first and second lead side surfaces of each of the leads, wherein the encapsulant material does not cover the second lead surface of each of the leads.

2. The integrated circuit chip package of claim 1 wherein the second end surface of each of the leads is uninterrupted and has a generally planar configuration.

3. The integrated circuit chip package of claim 2 wherein the second end surface of each of the leads extends generally perpendicularly between the reentrant portion extending within the first lead side surface thereof and the reentrant portion extending within the second lead side surface thereof.

4. The integrated circuit chip package of claim 2 wherein the second end surface of each of the leads is not covered by the encapsulant material.

5. The integrated circuit chip package of claim 1 wherein the reentrant portions of the die pad and the leads each comprise a recess.

6. The integrated circuit chip package of claim 1 wherein:

first and second reentrant portions extend fully around the side surface of the die pad in a manner facilitating the formation of a peak; and

first and second reentrant portions extend within at least portions of the first end surface and the first and second lead side surfaces of each of the leads in a manner facilitating the formation of a peak.

7. The integrated circuit chip package of claim 1 wherein the die pad has a generally quadrangular configuration, and the die pad side surface includes at least four die pad side surface portions.

8. The integrated circuit chip package of claim 7 wherein at least two connectors are integrally connected to respective ones of a corresponding pair of the die pad side surface portions, and the reentrant portion of the die pad extends through each of the connectors.

9. The integrated circuit chip package of claim 1 wherein the second die pad surface of the die pad is not covered by the encapsulant material.

10. The integrated circuit chip package of claim 1 wherein a portion of the connector is not covered by the encapsulant material.

11. The integrated circuit chip package of claim 1 wherein the at least one reentrant portion extending within at least portions of the first end surface and the first and second lead side surfaces of each of the leads further comprises:

a first reentrant portion extending within the first lead side surface from the first end surface to the second end surface;

a second reentrant portion extending within the second lead side surface from the first end surface to the second end surface; and

a third reentrant portion extending within the first end surface from the first lead side surface to the second lead side surface.

12. An integrated circuit chip package, comprising:

a die pad defining opposed first and second die pad surfaces, and a die pad side surface extending to at least the first die pad surface;

a plurality of leads disposed in spaced relation to the die pad, each of the leads defining opposed first and second lead surfaces, first and second lead side surfaces which each extend to at least the first lead surface, a first end portion defining a first end surface which extends to at least the first lead surface, and a second end portion defining an uninterrupted second end surface which extends between the first and second lead surfaces;

a reentrant portion extending within at least a portion of the die pad side surface;

a reentrant portion extending within at least portions of only the first end surface and the first and second lead side surfaces of each of the leads, the uninterrupted second end surface of each of the leads further extending between the reentrant portion disposed within first lead side surface thereof and the reentrant portion disposed within the second lead side surface thereof, the reentrant portions of the die pad and the leads being used for enhancing the connection between the die pad, the leads, and an encapsulant material applied to the die pad and the leads; and

an integrated circuit die attached to the first die pad surface of the die pad and electrically connected to the first lead surfaces of at least some of the leads;

the encapsulant material being applied to at least portions of the integrated circuit die, the first die pad surface and the die pad side surface of the die pad, and the first lead surface, the first end surface, and the first and second lead side surfaces of each of the leads, wherein the encapsulant material does not cover the second lead surface of each of the leads.

13. The integrated circuit chip package of claim 12 wherein the second end surface of each of the leads has a generally planar configuration.

14. The integrated circuit chip package of claim 13 wherein the second end surface of each of the leads has a planar configuration.

15. The integrated circuit chip package of claim 14 wherein the second end surface of each of the leads extends perpendicularly between the reentrant portion extending within the first lead side surface thereof and the reentrant portion extending within the second lead side surface thereof.

16. The integrated circuit chip package of claim 13 wherein the second end surface of each of the leads extends generally perpendicularly between the reentrant portion extending within the first lead side surface thereof and the reentrant portion extending within the second lead side surface thereof.

17. The integrated circuit chip package of claim 13 wherein the second end surface of each of the leads is not covered by the encapsulant material.

18. The integrated circuit chip package of claim 12 further comprising at least one connector integrally connected to the die pad side surface of the die pad and at least partially covered by the encapsulant material, the reentrant portion which extends within the die pad side surface extending through the connector.

19. The integrated circuit chip package of claim 18 wherein the die pad has a generally quadrangular configuration, and the die pad side surface includes at least four die pad side surface portions which each include the reentrant portion extending therein.

20. The integrated circuit chip package of claim 19 wherein at least two connectors are integrally connected to respective ones of a corresponding pair of the die pad side surface portions, and the reentrant portion which extends within the die pad side surface portions extends through each of the connectors.

21. The integrated circuit chip package of claim 12 wherein the second die pad surface of the die pad is not covered by the encapsulant material.

22. An integrated circuit chip package, comprising:

a die pad defining opposed first and second die pad surfaces, and a die pad side surface extending to at least the first die pad surface;

a plurality of leads disposed in spaced relation to the die pad, each of the leads defining opposed first and second lead surfaces, first and second lead side surfaces which each extend to at least the first lead surface, a first end portion defining a first end surface which extends to at least the first lead surface, and a second end portion defining an uninterrupted second end surface which extends between the first and second lead surfaces;

means extending within at least a portion of the die pad for enhancing the connection between the die pad and an encapsulant material applied thereto;

means extending within at least portions of only the first end surface and the first and second lead side surfaces of each of the leads for enhancing the connection between the leads and an encapsulant material applied thereto, the uninterrupted second end surface of each of the leads further extending between the connection enhancement means extending within each of the first and second lead side surface thereof; and

an integrated circuit die attached to the first die pad surface of the die pad and electrically connected to the first lead surfaces of at least some of the leads;

the encapsulant material being applied to at least portions of the integrated circuit die, the first die pad surface and the die pad side surface of the die pad, and the first lead surface, the first end surface, and the first and second lead side surfaces of each of the leads, wherein the encapsulant material does not cover the second lead surface of each of the leads.

23. The integrated circuit chip package of claim 22 wherein the connection enhancement means of the die pad extends within the die pad side surface thereof.

24. The integrated circuit chip package of claim 23 wherein the die pad has a generally quadrangular configuration, the die pad side surface includes at least four die pad side surface portions, and the connection enhancement means of the die pad extends within each of the at least four die pad side surface sections of the die pad.

25. The integrated circuit chip package of claim 24 wherein the connection enhancement means of each of the leads comprises a recess extending within at least portions of only the first end surface and the first and second lead side surfaces thereof, and the connection enhancement means of the die pad comprises a recess extending within each of the at least four die pad side surface sections thereof.

26. The integrated circuit chip package of claim 24 wherein the connection enhancement means of each of the leads comprises a peak extending along at least portions of only the first end surface and the first and second lead side surfaces thereof, and the connection enhancement means of the die pad comprises a peak extending along each of the at least four die pad side surface sections thereof.

27. An integrated circuit chip package, comprising:

a die pad defining opposed first and second die pad surfaces, and a die pad side surface extending to at least the first die pad surface;

at least one connector integrally connected to the die pad;

a plurality of leads, wherein all of the leads in the integrated circuit chip package are electrically isolated from the die pad and the connector, each of the leads defining opposed first and second lead surfaces, and a lead side surface which extends to at least the first lead surface;

a reentrant portion extending within at least a portion of the die pad side surface;

a reentrant portion extending within at least a portion of the lead side surface of each of the leads, the reentrant portions of the die pad and the leads being used for enhancing the connection between the die pad, the leads, and an encapsulant material applied to the die pad and the leads; and

an integrated circuit die attached to the first die pad surface of the die pad and electrically connected to the first lead surfaces of at least some of the leads;

the encapsulant material being applied to at least portions of the integrated circuit die, the connector, the first die pad surface and the die pad side surface of the die pad, and the first lead surface and the lead side surface of each of the leads, wherein the encapsulant material does not cover the second lead surface of each of the leads.

28. The integrated circuit chip package of claim 27 wherein the reentrant portion of the die pad extends fully around the die pad side surface and through the connector.

29. The integrated circuit chip package of claim 27 wherein, the second die pad surface of the die pad is not covered by the encapsulant material.

30. The integrated circuit chip package of claim 27 wherein a portion of the connector is not covered by the encapsulant material.

31. The integrated circuit chip package of claim 27 wherein:

the lead side surface includes first and second lead side surfaces which each extend to at least the first lead surface, a first end surface which extends to at least the first lead surface, and a second end surface which extends between the first and second lead surfaces; and

the reentrant portion of each of the leads extends within at least portions of the first end surface and the first and second lead side surfaces thereof.

32. The integrated circuit chip package of claim 31 wherein the second end surface of each of the leads is not covered by the encapsulant material.

33. The integrated circuit chip package of claim 27 wherein the connector includes an anchor which is at least partially covered by the encapsulant material.

34. An integrated circuit chip package, comprising:

a die pad defining opposed first and second die pad surfaces;

at least one connector integrally connected to the die pad;

a plurality of leads, wherein all of the leads in the integrated circuit chip package are electrically isolated from the die pad and the connector, each of the leads defining opposed first and second lead surfaces;

a lip extending along at least a portion of the die pad;

a lip extending along at least a portion of each of the leads, the lips of the die pad and the leads being used for enhancing the connection between the die pad, the leads, and an encapsulant material applied to the die pad and the leads; and

an integrated circuit die attached to the first die pad surface of the die pad and electrically connected to the first lead surfaces of at least some of the leads;

the encapsulant material being applied to at least portions of the integrated circuit die, the connector, the first die pad surface and the lip of the die pad, and the first lead surface and the lip of each of the leads, wherein the encapsulant material does not cover the second lead surface of each of the leads.

35. The integrated circuit chip package of claim 34 wherein the lip extends fully around the die pad.

36. The integrated circuit chip package of claim 34 wherein the second die pad surface of the die pad is not covered by the encapsulant material.

37. The integrated circuit chip package of claim 34 wherein a portion of the connector is not covered by the encapsulant material.

38. The integrated circuit chip package of claim 34 wherein the connector includes an anchor which is at least partially covered by the encapsulant material.

39. An integrated circuit chip package, comprising:

a die pad defining opposed first and second die pad surfaces and a die pad side surface, the die pad side surface including a lip which is adjacent to the first die pad surface;

at least one connector integrally connected to the die pad;

a plurality of leads, wherein all of the leads in the integrated circuit chip package are electrically isolated from the die pad and the connector, each of the leads defining opposed first and second lead surfaces and a lead side surface, the lead side surface of each of the leads including a lip which is adjacent to the first lead surface thereof; and

an integrated circuit die attached to the first die pad surface of the die pad and electrically connected to the first lead surfaces of at least some of the leads;

the encapsulant material being applied to at least portions of the integrated circuit die, the connector, the first die pad surface and the lip of the die pad, and the first lead surface and the lip of each of the leads, wherein the encapsulant material does not cover the second lead surface of each of the leads.

40. The integrated circuit chip package of claim 39 wherein:

the lip extends fully around the die pad;

the second die pad surface of the die pad is not covered by the encapsulant material; and

a portion of the connector is not covered by the encapsulant material.