Enhancing MOSFET performance by optimizing stress properties

• US 8,318,570 B2
• Filed: 12/01/2009
• Issued: 11/27/2012
• Est. Priority Date: 12/01/2009
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Zhang, Ying
• Primary Examiner(s): Lebentritt, Michael
• Application Number:
  US12/628,724
• Publication Number:
  US 20110127588A1
• Time in Patent Office: 1,092 Days
• Field of Search: 438230-233, 438/303, 438/305, 257/E21.246, 257/345, 257/396, 257/437, 257/443, 257/633, 257/27.064, 257/29.063
• US Class Current: 438/303
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas fainted in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.

Claims

1. A method for improving performance of a semiconductor device, comprising:

forming gate structures on a substrate having a spacing therebetween, the gate structures being formed in an operative relationship with active areas formed in the substrate;

forming a stress liner on the gate structures; and

applying an angled ion implantation such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.

2. The method as recited in claim 1, further comprising forming dummy structures to provide the shadowing effect for gate structures at an end of an array.

3. The method as recited in claim 1, wherein the gate structures include gate structures for N-type field effect transistors.

4. The method as recited in claim 1, wherein the adjacent structures include a block mask.

5. The method as recited in claim 4, wherein the block mask covers a P-type field effect transistor and applying the angled ion implantation includes adjusting an angle of attack to overcome the block mask to direct ions at the vertical surfaces of the stress liner.

6. The method as recited in claim 1, wherein the angled ion implantation is performed in a single ion implantation step.

7. The method as recited in claim 1, wherein the angled ion implantation is performed in a plurality of stages such that implantation parameters are adjustable in accordance with the adjacent structures.

8. The method as recited in claim 1, wherein the angled ion implantation includes inert ion species.

9. The method as recited in claim 1, wherein the gate structures include gate structures for fin field effect transistors.

10. A method for improving performance of a transistor, comprising:

forming gate structures on a substrate having a spacing therebetween, the gate structures being formed in an operative relationship with active areas formed in the substrate;

forming dummy structures at a periphery of an array of the gate structures;

forming a stress liner on the gate structures and the dummy structures, the stress liner including vertically disposed portions on sidewalls of the gate structures and dummy structures; and

applying an angled ion implantation such that ions are directed at the vertically disposed portions of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.

11. The method as recited in claim 10, wherein the dummy structures provide the adjacent structures with a height and spacing equivalent to that of adjacent gate structures.

12. The method as recited in claim 10, wherein the gate structures include gate structures for N-type field effect transistors.

13. The method as recited in claim 10, wherein the adjacent structures include a block mask.

14. The method as recited in claim 13, wherein the block mask covers a P-type field effect transistor and applying the angled ion implantation includes adjusting an angle of attack to overcome the block mask to direct ions at the vertical surfaces of the stress liner.

15. The method as recited in claim 10, wherein the angled ion implantation is performed in a single ion implantation step.

16. The method as recited in claim 10, wherein the angled ion implantation is performed in a plurality of stages such that implantation parameters are adjustable in accordance with the adjacent structures.

17. The method as recited in claim 10, wherein the angled ion implantation includes inert ion species.