Micro-electromechanical system devices

• US 8,318,581 B2
• Filed: 11/18/2011
• Issued: 11/27/2012
• Est. Priority Date: 06/04/2008
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mueller, Karl-Heinz, Winkler, Bernhard, Gruenberger, Robert
• Primary Examiner(s): Yang, Minchul
• Application Number:
  US13/300,138
• Publication Number:
  US 20120061734A1
• Time in Patent Office: 375 Days
• Field of Search: 438/207, 438/422, 438/426, 438/428, 257/E21.295, 257/696
• US Class Current: 438/422
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 2203/0742 Interleave, i.e. simultaneously forming the micromechanical structure and the CMOS circuit

Abstract

Micro-electromechanical system (MEMS) devices and methods of manufacture thereof are disclosed. In one embodiment, a MEMS device includes a semiconductive layer disposed over a substrate. A trench is disposed in the semiconductive layer, the trench with a first sidewall and an opposite second sidewall. A first insulating material layer is disposed over an upper portion of the first sidewall, and a conductive material disposed within the trench. An air gap is disposed between the conductive material and the semiconductive layer.

Claims

1. A method of manufacturing a semiconductor chip comprising MEMS devices, the method comprising:

forming a semiconductive layer over a substrate, the substrate comprising a buried oxide layer;

forming a first trench in the semiconductive layer, the first trench exposing the buried oxide layer;

forming an insulating material layer over a first sidewall and an opposite second sidewall of the first trench and exposed buried oxide layer;

filling the first trench with a conductive material; and

forming an air gap by removing the insulating material layer from the second sidewall, the air gap being formed around top and bottom surfaces of the semiconductive layer.

2. The method of claim 1, wherein forming the semiconductive layer comprises:

selectively depositing a first semiconductive layer;

selectively doping the first semiconductive layer to form a first highly doped region;

selectively depositing a second semiconductive layer; and

selectively doping the second semiconductive layer to form a second highly doped region, wherein the second highly doped region is disposed above the first highly doped region.

3. The method of claim 2, wherein the first highly doped region comprises resonator electrode regions of the MEMS devices.

4. The method of claim 3, wherein the first highly doped region comprises collector regions of bipolar transistors.

5. The method of claim 2, wherein the second highly doped region comprises contacts and/or collector regions of bipolar transistors.

6. The method of claim 2, further comprising:

forming base and emitter regions of bipolar transistors on the second semiconductive layer.

7. The method of claim 2, further comprising:

forming source/drain regions, source/drain extension regions, and channel regions of CMOS transistors on the second semiconductive layer.

8. The method of claim 1, further comprising:

forming an isolation trench by forming a second trench in the semiconductive layer, the first trench and the second trench formed using a common etch process, the second trench being narrower than the first trench, wherein forming the insulating material fills the second trench.

9. The method of claim 1, further comprising:

forming a trench capacitor by forming a third trench in the semiconductive layer, the first trench and the third trench formed using a common etch process, the third trench being about identical to the first trench.

10. A method of manufacturing a semiconductor chip comprising a MEMS device, the method comprising:

epitaxially growing a lightly doped first semiconductive layer over a substrate, the substrate comprising a buried oxide layer;

doping the first semiconductive layer to form a first highly doped region;

epitaxially growing a lightly doped second semiconductive layer on the first semiconductive layer;

forming first and second trenches in the first and second semiconductive layers, the first and second trenches exposing the buried oxide layer;

forming an insulating layer over the first and second trenches, wherein the insulating layer fills the second trench;

filling the first trench with a conductive material; and

forming an air gap in the first trench by removing the insulating layer, the air gap being formed on a top surface of the second semiconductive layer and a top surface of the substrate.